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International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

International audience; We present experimental and simulated J-V characteristics of Metal/Insulator/Semiconductor (MIS) junctions aiming at improving the contact resistivity for advanced CMOS nodes. We show that an Atomic Layer Deposition (ALD)-based Al2O3 process may induce a native silicon oxide regrowth leading to an additional tunneling resistance in series. A modelling-based analysis of Metal/Insulator/Insulator/Metal (MIIS) contacts, including the potentially beneficial interfacial dipole, provides a new outlook on high-kappa/SiO2 bilayers for low resistivity contacts.

The abundance of work on SiGe based devices demonstrates the importance of compositional characterization of such materials. However, SIMS characterization of SiGe layers often suffers from matrix effects due to non-linear variation of ionization yields with Ge content. Moreover, the presence of oxide in these layers would definitely increase the difficulty to obtain quantitative profiles by SIMS. We highlight here the improvements brought by the extended Full Spectrum protocol, presented in previous works and allowing minimization of matrix effects in SiGe matrices compared with more classic protocols. This results in more accurate depth profiles, and thus brings better comprehension of the behavior of intrinsic and doped layers under dry or wet oxidizing.

The resistivity of copper interconnect metallization can be influenced by low levels of contaminant (Cl, S, etc.) resulting from the electrochemical deposition process. ToF-SIMS imaging was used to investigate the distribution of contamination in Cu grains. ToF-SIMS images of full sheet Cu samples were compared with images of Cu lines in patterned test structures. An ION-TOF ToF-SIMS V instrument was used to acquire the images, and the results using Ga and Bi sources are compared. Cs sputtering was used to remove the surface oxide layer and to enhance the emission of Cl − ions. Enhanced Cl − emission is seen at the grain boundaries in full sheet samples and differences in Cl − emission are observed for Cu lines of different widths.

Electrical, electrooptical, mechanical, and microstructural characterizations explain why the leakage currents in advanced Cu/ultralow-interconnects can change from bulk (3-D) to mostly interfacial (2-D) above 150degC. A physical model consistent with all these results is proposed.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

Phase change memory technology is considered as one of the most promising resistive memory solution. One issue, however, is the high electrical current required to reset the information. Indeed large energies are mandatory for amorphization of the crystalline phase change material. It has been demonstrated that energies can be highly decreased by reduction of the active volume and confinement of the phase change material. To do so, phase change materials deposition route with high filling capacity is needed. Atomic Layer Deposition (ALD) is well known for its high conformity. However, such a process is still a challenge for phase change materials such as Ge x Sb y Te z (GST). In this work, (i) ALD GST films are processed and characterized and (ii) realisation of phase change memory devices using ALD GST is demonstrated on 200mm wafers.

In this work we investigate the correlation between hydrogen content and leakage current through the Al 2 O 3 layers of TANOS memories. We put in evidence that retention of TANOS memories is improved with the decrease of H concentration in the Al 2 O 3 layer. Using atomistic simulations consolidated by detailed Al 2 O 3 physico-chemical analyses, we find that interstitial H produces a midgap trap likely to participate to trap assisted conduction.

In this work, we use atomistic simulation, consolidated by a detailed Al 2 O 3 physico-chemical material analysis, to investigate the origin of traps in Al 2 O 3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al 2 O 3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.

This paper presents a detailed comparative study of the switching characteristics of resistive memory devices, with NiO or HfO 2 active materials and Pt electrodes, based on identical integration schemes. Material screening and qualification are performed using structural and composition analyses. Preliminary electrical investigations outline the non-polar switching behavior of both HfO 2 and NiO devices. Then, by using a specific test setup, we present a systematic comparative study of HfO 2 and NiO devices, clearly showing the tunability of the electrical characteristics with material type and process. HfO 2 devices lead to largest High Resistance State/Low Resistance State ratios and higher forming voltages compared to NiO cells, while reset voltages are similar. Data retention of both materials show highly stable Low Resistance State state, while High Resistance State increases over time under 85°C baking.

(Invited); International audience; We have studied the Cyclic / Deposition Etch (CDE) of Si with either SiH4 or SiH2Cl2 + HCl for the deposition steps and HCl for the etch steps. The HCl etch rate of poly-Si is indeed several times higher than the one of mono-crystalline Si. We have demonstrated that at 650{degree sign}C, 300 Torr, SiH4 / HCl CDE processes were selective versus SiO2 for high numbers of cycles. We have also showed that 20 Torr, SiH2Cl2 + HCl - based CDE processes enabled to selectively grow 85 - 140 nm thick Si Raised S/Ds on each side of multi-bridge channel FETs with Si3N4 internal spacers. Finally, we have demonstrated the efficiency of various CDE process in suppressing mushrooming on top of un-capped poly-Si gates of FD-SOI FETs after the formation of Si RSD ({116} facets at the boundary between the gate stack and the S/D regions and moat recess, however).

In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics at high temperature is suggested.

International audience; The annealing of chlorine-doped polycrystalline CdTe films leads to the occurrence of an abnormal grain structure with the formation of both primary and secondary grains, the latter being larger and growing at the expense of the former. The spatial distribution of dopants and defects has been investigated within both types of grains by time-of-flight secondary-ion-mass spectroscopy imaging and spatially resolved cathodoluminescence. It is found that chlorine atoms similarly segregate in the vicinity of grain boundaries in both primary and secondary grains, whereas chlorine donors are homogeneously distributed away from grain boundaries. It is shown that, contrary to primary grains, secondary grains exhibit specific concentration processes around grain boundaries, such as cadmium vacancy accumulation and dislocation piling up. The existence of long-range stresses around grain boundaries only within secondary grains is also evidenced and attributed to piezoelectric effects. Grain boundaries thus act as getters for dopants and defects by draining them from the interior of secondary grains. These physical mechanisms emphasize efficient purifying effects associated with the beneficial formation and growth of secondary grains within an abnormal grain structure as induced by annealing. The depicted processes can be applied to a wide variety of polycrystalline compound semiconductors and can find direct applications in the field of solar cells based on these materials.

In this work, we studied Excimer Laser Annealing at 308 nm with 180 ns pulse duration on Phosphorus and Boron implanted in Germanium, with or without Pre-Amorphization Implant (PAI) and co-implant. Using an industrial tool, experimental results show that we can achieve electrical activation levels up to 1.2×1020 cm−3 for P implant in Ge, which is the highest level regarding the appropriate mobility model. With the B implanted samples, we obtained an electrical activation level higher than 1×1020 cm−3 which is the better results obtained whithout PAI [1]. Melt thresholds were determined to be 0.65 J/cm² in amorphized Germanium (a-Ge) and 0.95 J/cm² in crystalline Germanium (c-Ge). With P, the best activation was obtained after a complete melt of the amorphous layer and the amorphous / crystalline (a/c) interface, necessary to obtain a perfectly recrystallized layer. In the case of B, we found a better activation in the submelt regime compared the melt one, and no contribution on the electrical activation with PAI was observed.

In this work, the influence of a pre-amorphization implant (PAI) combined with a single-step spike anneal on the junction formation in Germanium is inverstigated, both for n-type dopant with Phosphorus (P) as well as for p-type dopant Boron (B). The experiments were performed on a 1.5µm Germanium (Ge) epi-layer onto 200mm Silicon (Si) substrate. After implantation both with or without PAI, the dopant activation was achieved using a single step, conductive, spike anneal (ranging 550oC–900oC) in a ASM Levitor® system. Junction depth (Xj) and electrical activation levels (N act ) were characterized using secondary-ion-mass spectroscopy (SIMS) and sheet resistance Rs measurements. The results show that the combination of the high ramp rates with single step spike anneal on the one hand and PAI on the other hand, improved junctions characteristics compared to standard implant and RTP (Rapid Thermal Processing) conditions. The SIMS results show a reduction of junction depth for pre-amorphized junction after activation annealing up to 20% with P and 42% with B at 5×1018 cm−3 dopant concentration. In addition, electrical activation levels up to 4,95×1020 cm−3 were achieved for the p-type implants.

This work deals with the development of resistive memories based on oxides and their integration into the interconnection levels. The paper is focused on the screening of different dielectric oxides (metallic or not) showing resistive switching properties in order to lead to the highest performance resistive memories. Nickel oxide which is the most studied material in the literature is compared to other binary metallic oxides. In parallel, cells with silicon based dielectrics and Cu electrodes were developed. Electrical results allowed a comparison between the 3 main mechanisms observed in resistive memories based on oxides. Moreover, a specific resist flowing process and ion beam etching were optimized in order to limit metallic residues on memory cell side walls and prevent short-circuiting.

International audience; We have studied the structural properties of tensile-strained Si layers grown on polished Si1−xGex virtual substrates (x = 0.2, 0.3, 0.4 and 0.5) as a function of their thickness. We have used specular X-Ray Reflectivity to gain access to the sSi layer thickness (in-between 10 and 37 nm for sSi on Si0.8Ge0.2 and Si0.7Ge0.3, in-between 6 and 28 nm for sSi on Si0.6Ge0.4 and in-between 5 and 24 nm for sSi on Si0.5Ge0.5). The surfaces of the sSi layers (grown at 700 °C, 2660 Pa with SiH2Cl2) are characterized by a slight resurgence of the surface cross-hatch. We obtained surface root mean square roughness in-between 0.3 and 0.4 nm. The interfaces in-between sSi and SiGe are abrupt, as illustrated by High Resolution–Transmission Electron Microscopy and by the Ge decay profile in Secondary Ions Mass Spectrometry: 0.73–1.06 nm/decade. UV-Raman spectroscopy has shown that the tensile stress in the sSi layers decreased very slightly as the sSi layer thickness increased. Mean values, 1.32, 1.87, 2.58 and 3.15 GPa, are close to the ones theoretically expected for fully pseudomorphic sSi layers on Si0.8Ge0.2, Si0.7Ge0.3, Si0.6Ge0.4 and Si0.5Ge0.5 are close to the ones theoretically expected for fully pseudomorphic sSi layers. They are also very similar to those experimentally found in X-Ray Diffraction for sSi on Si0.8Ge0.2 and Si0.7Ge0.3: 1.32 GPa and 1.95 GPa. We have also studied, thanks to Secco etching, the defects present in these sSi layers. The Threading Dislocations Density (TDD) slightly increases from 1 up to 3 × 105 cm− 2 as the sSi thickness increases. It is however rather close to the TDD associated to the SiGe VS underneath (1–2 × 105 cm− 2). Meanwhile, the Line defects (i.e. stacking faults and/or misfit dislocations) Linear Density (LLD) increased from 0 up to 400, 700, 800 and 300 cm− 1 as the sSi layer thickness on Si0.8Ge0.2, Si0.7Ge0.3, Si0.6Ge0.4 and Si0.5Ge0.5 increased from 5–10 up to 24–37 nm. Were we to adopt as critical thickness the ones for which the LLD exceeds 50 cm− 1, we would find values around 12 nm, 10.5 nm, 6.5 nm and 9 nm for Ge contents equal to 0.2, 0.3, 0.4 and 0.5, respectively. It would seem that the LLD depends on the Ge concentration but also on the surface roughness and apparently the surface preparation prior to re-epitaxy.

Electrical, electro-optical, mechanical and microstructural characterizations explain why the leakage currents in advanced Cu/ultra-low K interconnects can change from bulk (3D) to mostly interfacial (2D) above 150degC. A physical model consistent with all these results is proposed

With the scaling down of copper interconnects, the importance of interface engineering becomes more and more crucial. In this paper, we have studied the influence of the diffusion barriers on the electrical performance and dielectric reliability of porous ULK/Cu interconnects, in comparison with a reference dense SiCOH dielectric. The best reliability for the porous ULK is obtained with the thicker barrier, consisting of CVD TiN. With this barrier; the porous ULK can even outperform the dense dielectric in terms of time to failures and dielectric breakdown in certain cases. For the TaN barrier, an H/sub 2/ plasma after etch improves the breakdown voltage up to 34%. A voiding at the top Cu comers after storage in the 110/spl deg/C-150/spl deg/C range under N/sub 2/ has been identified as a possible contribution to the fracture of the SiCN top capping layer. Therefore the Cu itself is critical for the dielectric reliability.

The tensile creep and creep rupture properties of beta-phase Zircaloy-2 are studied under vacuum in the temperature and stress range 1300–1550 K and 0.5–2 MN/m2. The new results are compared with previously reported uniaxial and biaxial data. A small, but systematic difference is noted between the uniaxial and biaxial creep data and reasons for this discrepancy are discussed.

A technique is described for the manufacture of solid ZrO 2 pellets from powder. Creep tests have been performed on the material at temperatures in excess of 1400 K where the tetragonal ZrO 2 phase is stable and in the stress and temperature range where the predominant deformation mode is expected to be flow by grain-boundary diffusion. Since there are no disposable parameters in the predicted flow equation, it enables an estimate of diffusivities to be made from the flow characteristics. Interpretation of results is complicated by contributions from stress-enhanced sintering of the residual porosity remaining from the manufacturing process and a new way is suggested of analysing creep data in such materials. The probable contribution by intragranular diffusional flow between dislocations is also assessed and its influence on data analysis at low strains is calculated. No available tracer diffusion coefficient exists to compare with the present results although comparison with other reported diffusivities for other oxide systems indicates agreement when they are normalized for differences in melting temperature.

The creep of uranium dioxide has been investigated as a function of grain size. At high stresses, when creep is controlled by dislocation movement, grain boundaries exert a strengthening effect and this strengthening is correlated with the Hall-Petch equation. The degree of strengthening diminishes with increases in temperature. At lower stresses, when creep is controlled by mass transport, grain boundaries exert a weakening effect owing to the reduction in diffusion path length as grain size is reduced. In this range behaviour is correlated with the Nabarro-Herring equation with stress σ replaced by an effective stressσ E=σ−σ0 whereσ 0 is a threshold stress for diffusional creep associated with the limitation of the ability of boundaries to emit and absorb vacancies.σ 0 appears to decrease as grain size is increased.

In this paper, fabrication of nanocomposite thin films with introduction of fullerene (C60) molecules in PolyMethyl MethAcrylate resist (PMMA) was investigated from a material and electrical point of view. The effective inclusion of C60 molecules in the samples was characterized by using UV-vis and Tof-SIMS instruments. The modified resist PMMA:C60 was also studied with Thermal analysis (TGA, DSC) where modification of physical properties is reported. Films were included in MIS and MIM devices and results on non volatile trapping of C60 doped PMMA are presented. Moreover, e-beam exposure tests showed that PMMA:C60 active layers for memory devices, were scalable in size.

We have investigated the p- and n-type dopants in thin SGOI (20 nm) material obtained by Ge enrichment. The samples are doped with either BF2 or arsenic or phosphorus and then annealed with either a spike or a 15 s rapid thermal annealing in a temperature range of 850-1050 °C. We have observed that sheet resistance (Rsh) obtained in SGOI for p-type is approximately independent of annealing conditions. In addition, these values are lower than the SOI (20 nm) reference. Result reveals that almost all BF2 atoms remain in SGOI substrate giving rise to low Rsh, whereas dopant out diffuses and segregates in SOI. In contrast, Rsh measured with arsenic and phosphorus implanted SGOI samples is higher than SOI.

Based on electrical measurements and transmission electron microscopy (TEM) imaging, we propose an explanation for the electron and hole mobility degradation with gate length reduction in metal–oxide–semiconductor field effect transistors (MOSFETs). We demonstrate that ion implantation, normally used for source/drain doping, is responsible for transport degradation for short-channel devices. Implantation impact on electrons and holes mobility was investigated both on silicon-on-insulator (SOI) and tensile strained silicon-on-insulator (sSOI) substrates. Wafers with ultrathin Si films (from 8 to 35 nm) were Ge implanted at 3 keV and various concentrations (from 5×1014 to 2×1015 atoms cm−2), then annealed at 600 °C for 1 h. Secondary ion mass spectrometry enabled us to quantify the Ge-implanted atoms concentrations. The end-of-range defects impact on mobility was investigated with the pseudo-MOSFET technique. Measurements showed a mobility decrease as the implantation dose increased. We demonstrated that sS...

The integration of a monolithic antiparallel diode into the inactive cathode bond-pad area of a gate turnoff thyristor (GTO) has been investigated with computer modelling followed by experimental work, using as a vehicle the BTV60, a 120A GTO optimised for AC motor control. It is shown that this is feasible and is especially suitable for second generation GTO technology (fine interdigitation, unshort-circuited anode, lightly gold-killed), with the diode having the right characteristics in forward voltage drop and reverse recovery. The resulting devices performed well in tests and may lead to considerable simplification and cost reduction in motor control circuits.