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This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

A dual-shutter MEMS variable optical attenuator (VOA) is designed for advanced tuning functions such as linear attenuation relationship and simultaneous coarse and fine tunings. The mechanism behind is to take advantage of the additional shutter to render one more degree of freedom for attenuation adjustment. Although dual-shutter VOAs with asymmetric functionalities have been reported before, these intrinsic capabilities owing to asymmetry have not been extensively investigated. In experiment, the fabricated VOA device has demonstrated a linear tuning over a 20-dB range with respect to the driving voltage of one shutter, and it has also realized simultaneously coarse tuning (2.5 dB/V) and fine tuning (0.1 dB/V) by the two shutters. Ideally, the tuning can start from any available working point, linear to any controlling parameter, at any slope of linearity, and with any tuning resolution. Theoretical attenuation model has also been developed to provide a roadmap for the VOA design and choice of working point. An interesting finding is that over a certain range the linear attenuation can be obtained by moving a fixed aperture rather than by reducing the aperture size, which greatly relaxes the difficulty of shutter position control. The measured results match well with the theoretical data, implying the possibility of developing a look-up table to locate the shutter positions quickly. The dual-shutter VOA accomplishes these features without the need of high-precision control systems and therefore gives a structure-based rather than a control-system-based solution, clearly advantageous over the previously developed VOAs.

The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided.

The curing conditions and material properties such as the TCE (thermal coefficient of expansion), T/sub g/ (glass transition temperature), flexural storage modulus, tangent delta, and moisture content of nine different underfill materials from three different vendors are measured. Their flow rate and the effect of moisture content on mechanical (shear) strength in solder bumped flip chips on organic substrate are also determined experimentally. Furthermore, their effects on the electrical performance (voltage) of functional flip chip devices on organic substrate are measured. Finally, a simple methodology is presented for the selection of underfills from the measurement results of these nine different underfill materials.

An electrically and thermally optimized plastic ball grid array (PBGA) package, called new and useful ball grid array (NuBGA) is presented. NuBGA is a cavity down package with a metal heat spreader covering the entire back-side of the chip. The heat spreader is laminated with a single-core double-sided organic substrate. Super electrical performance is achieved by using the split-wrap-around (SWA) or split-via-connection (SVC) design concepts. All traces on the core substrate are designed into /spl mu/-stripline and co-planar stripline structures. In this paper, the focus is on (1) the unique design concepts; (2) the electrical measurement; (3) the electrical analysis; (4) the electrical performance comparison with other standard packages.

The explosive growth of high‐density packaging has created a tremendous impact on the electronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip Scale Packaging (CSP), Direct Chip Attach (DCA), and flip‐chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. In this paper, they will be briefly discussed.

The thermal, mechanical, and vibrational responses of flip chip and plastic ball grid array (PBGA) solder joints have been determined in this study. The effects of overload environmental stress factors on the mechanical responses of the solder joints have been determined by bending and twisting experiments. The effects of shipping environmental stress factors on the vibrational responses of the solder joints have been determined by out-of-plane vibration experiments. Also, the thermal fatigue behavior of solder joints have been investigated by nonlinear finite element (FE), Coffin-Manson, and fracture mechanics methods.

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

A bio-microfluidic cartridge has been developed with integrated reservoir and valves for Lab on a chip (LOC) applications, e.g. extracting DNA (Deoxyribonucleic Acid) from human blood. A combination of different materials such as thermoplastic and elastomer are used to fabricate the microfluidic cartridge. A conical shape reservoir with thin membrane sealing is designed to have minimum dead volume in the reservoir after dispensing completely into the chip. An external actuation is used to apply pressure on the thin rubber membrane to push the fluid from the reservoir to the chip and to output collector. The external actuation pushes the fluid through the pin valve and the fluid flow is proportional to the actuation speed. Material selections and package optimization have done to maximize the performance of the cartridge functionality. Different mixing ratio of PDMS (Polydimethylsiloxane) material based on elongation has been tried to select the membrane to seal the reservoir. To contain the reagents inside the reservoir different thermoplastic material has been tried over the elastomer material. Bonding of similar and dissimilar material is studied for fluidic channel layer selection. Extraction of DNA/RNA (Ribonucleic Acid) from blood sample is tried and sufficient quantity of DNA has been extracted from this cartridge for PCR (Polymer Chain Reaction) amplification and detection.

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of silicon (~2.5 times10-6/degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.

The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore's law, the packaging is challenged to integrate and shrink. Chips first or embedded chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level. A detailed mechanical and structural analysis of the package in terms of the die thickness, wafer size and warpage is presented. The package format is suitable for stacking multiple die in 3D format and 2D format. The paper also deals with characterization of the materials and the process integration of the multidie wafer level packaging. Initial reliability results of the package are also presented.

A high speed shear test of solder ball at different shear angles has been developed and investigated for SnAgCu solder balls. The objective of the test is to introduce vertical loading component in the high speed shear test and to study intermetallic response of different solder balls. The shear test is performed at three angles of attack e. g. 3, 5 and 10 degree. The basic shear tester allow high speed shear tool movement of up to 4000 mm per second, and capture the load-displacement curve experienced by the shear tool. Using this setup, high-speed shear characterization has been carried out on microBGA sample with Sn3Ag0.5Cu and Sn1Ag0.5Cu solder on Ni/Au pad finish. In this paper, the effect of angle shear at high speed on these SnAgCu BGA balls is presented, with the details of load-displacement response and failure mode for these solder balls. Generally all the samples show changes in ductile-to-brittle failure as shear speed increases. The angled shear test lead to down shift of ductile-brittle transition to occur at lower shear speed with larger shear angle. It is found to improve sensitivity in revealing brittle failure for solder ball characterization.

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.

To study the effect of back grinding on the mechanical properties of the active side of the die, low-k stacked wafers were grinded to four different thicknesses of 500 mum, 300 mum, 150 mum, and 75 mum by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed using the Nanoindenter XP (MTS Corp. USA) on both the normal (no back grinding) and back grinded samples to analyze the failure loads, modulus, hardness and adhesive/cohesive strength, of the low-k stack. It is found that the back grinding process enhances the mechanical integrity of low-k stack as the back grinded low-k stack exhibited in terms of the higher failure load and cohesive and/or adhesive strength of grinded low-k stack than the normal low-k stack. The TEM cross-section analysis showed that the interfaces in the low-k stack of normal sample are wavy, whereas the interfaces in the low-k stack of back grinded samples are even, especially at the black diamond region. Significant densification of BD films is observed in the case of back grinded sample. Based on these results, it is believed that the thermo-mechanical stresses applied and/or generated during wafer back grinding process affect the microstructure and enhance the mechanical strength of the low-k stack.

An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D micro mirror is used for steering the beam from the source to the sample. A GRIN lens, fiber and micro mirror are assembled in a silicon optical bench. The assembled components are housed in the bio-compatible microinjection molded housing. The images obtained using this probe is studied with respect to probe assembly. Tolerance of GRIN lens placement, micro mirror placement on the substrate, deformation of the mirror, housing transparency and housing curvature are studied with respect to the final image from the probe. In this study it is found that a higher mirror curvature affects the depth of focus on the sample and mirror placement reduces the coupling efficiency during the optical assembly.

Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.

Polymer Optical Fiber (POF) optical modules are gaining momentum due to their applications in short distance communications. POFs offer more flexibility for plug and play applications and provide cost advantages. They also offer significant weight advantage in automotive and avionic networks. One of the most interesting field of application is home networking. Low cost optical components are required, since cost is a major concern in local and home networks. In this publication, a fast and easy to install, low cost solution for efficient light coupling in and out of Step Index- POF is explored. The efficient coupling of light from a large core POF to a small area detector is the major challenge faced. We simulated direct coupling, lens coupling and bend losses for step index POF using ZEMAX R optical simulation software. Simulations show that a lensed fiber tip particularly at the receiver side improves the coupling efficiency. The design is optimized for 85% coupling efficiency and explored the low cost fabrication method to implement it in the system level. The two methods followed for lens fabrication is described here in detail. The fabricated fiber lenses are characterized using a beam analyzer. The fabrication process was reiterated to optimize the lens performance. It is observed that, the fabricated lenses converge the POF output spot size by one fourth, there by enabling a higher coupling efficiency. This low cost method proves to be highly efficient and effective optical coupling scheme in POF communications.

There is an increasing demand for tunable lasers in telecommunications networks for test equipment, optical components and other applications. In DWDM systems, multiple data streams propagate concurrently on a single mode fiber. DWDM networks are based on a DFB lasers operating at a wavelength defined by ITU wavelength grid. Statistical variations associated with the manufacture of DFB laser results in yield losses. Continuously tunable external lasers are developed to overcome the limitations of DFB lasers. Various laser tuning mechanisms are being explored to provide external cavity tunable lasers to provide a stable single mode output. The packaged tunable laser source (TLS) for DWDM network also need to include several optical elements for isolation and data modulation like collimator, focusing lens, fiber pigtail, a modulator and output fiber segment. In this publication, we propose a novel semi integrated miniature high frequency tunable laser design based on Silicon Optical Bench (SiOB) concept. One of the mirrors is a movable MEMS structure changing the optical path length. We propose micro optical design between laser diode and the MEMS mirror for efficient optical coupling and side mode suppression. We also present the compatibility between the optical coupling and MEMS actuation range. We present the coupling efficiency results over the tuning range. We also propose a method of monitoring the output power of the tunable laser using waveguide coupler structures which are integrated in the silicon wafer and method of packaging in a miniature package compatible to the industry standard form factor.

Silicon Optical Bench (SiOB) is a popular solution for passive assembly of optical module. In order to realize an optical transmitter or receiver module, it is necessary to integrate high frequency optoelectronic components such as signal photodiodes (PD) or laser diodes (LD) onto the SiOB. In this way, the module's electrical and optical performances can be further improved, and a higher degree of miniaturization can be achieved. The challenge for this integration is not only on the assembly accuracy for the LD and PD, it required the design of low loss electrical interconnect at high frequency. However, the standard silicon substrate used in the SiOB has a high electrical loss especially at high frequency. This imposed a limitation on the electrical interconnection length between the optoelectronic components and their I/O interfaces. It is proposed here to design the electrical interconnection using a layer of SiO 2 sandwiched between two layers of metal layer. Simulations have demonstrated that by varying the thickness of the SiO 2 layer, an optimum electrical performance can be achieved.

Recent developments in the short distance communication have made polymer optical fibers (POF) an attractive product in the high speed data communication market. The requirement of a large bandwidth, low cost, light weight and flexibility in installation have placed them over the copper cables especially in applications like home networking and automotives. Since POFs are large core multimoded fibers, their band width is limited by intermodal dispersion. This confines POFs application to low data rate short distance communications. Restrictive mode launchers (RML) and higher order mode strippers placed in the data link helps to reduce the intermodal dispersion. The techniques used to implement these signal conditioners should be simple and cost effective to keep POFs attractive in the short distance communication. In this paper we explore the possibility of integrating the RML and mode stripping elements in the transmitter and receiver package itself. The pre-designed optical signal conditioning elements are projected to get molded in the plastic packages and are fiber plug in modules. This connector less package design, universal to any light source proposes to enhance the data rate and is widely manufacturable at an ease of installation and low cost.

A 12*12 stiffness matrix was obtained for the gull-wing lead and solder joint in a plastic quad flat pack (PQFP) surface-mount assembly, using a three-dimensional finite element method. Deformation of the composite structure for each imposed unit displacement (or rotation) was then obtained. It is shown that the whole-field stress distributions in the gull-wing lead provide a better understanding of their mechanical characteristics. The metallurgical response of the solder joints was not measured in this study. >

In this study, the effect of a very low level of doping of Ce on the SnAgCu solder is investigated. Emphasis is placed on the determination of the material properties (such as the temperature and strain rate dependent Young's modulus, yield stress, and ultimate strength) and the intermetallic compounds on OSP (organic solderability preservative) and NiAu (electroless Ni and immersion Au) FR-4 copper surface finishes of the new Sn3wt%Ag0.5wt%Cu0.019wt%Ce lead-free solder.

The objective of this paper is to point out the limitations and ròles of DNP (distance to neutral point) on predicting the solder‐joint thermal‐fatigue life of area‐array assemblies.

The stresses and strains in tape automated bonding (TAB) assemblies have been studied using a nonlinear three-dimensional finite-element method. Detailed stress distributions in the TAB assembly beam leads, polyimide rings, gold bumps, silicon chips, and solder joints are presented. Due to the flexibility of the beam lead and the unequal thermal expansion and stiffness difference of all the parts of the TAB assembly, the beam lead was subjected to the largest deformation. Bending of the silicon chip and printed circuit board was very small compared with that of the beam lead, because of their much larger section moments of inertia. Due to their small thickness, the TAB beam leads, unlike the case of conventional surface mount technology assemblies, are more likely to fail than the solder joints. There is excellent agreement between the analytically predicted and the experimentally observed failure mechanisms. The results presented should be useful in understanding and designing more reliable advanced surface-mount assemblies. >

Three very small microwave packages have been designed and fabricated. The hermeticity performance and reliability of these packages were evaluated. Package A has brazed leads and hence superior lead strength (lead tension and lead fatigue), but poor and inconsistent hermeticity yields. The leads of package B are sandwiched between the base and lid using the solder glass, so that the lead strength is not as good as that of the brazed leads. Furthermore, the sealed package is more susceptible to handling-related problems. The bending process caused microcracks along the sealing glass, which deteriorate the hermeticity of the package. The package C design incorporated the package A design and the side braze package design. The reliability of this package meets the JAN-S requirements as well as other military standard specifications. The performance of the package is also acceptable for high-frequency microwave applications. The results indicate that packages designed with closely matched coefficient of linear thermal expansion materials provide reliable hermetic packages. >

Vibration frequencies of soldered and unsoldered leads of surface-mount wide and narrow small outline integrated circuits (SOICs), plastic leaded chip carriers (PLCCs), and plastic quad flat packs (PQFPs) are calculated using the finite-element method. The corresponding mode shapes of the leads and solder joints are also provided for a better understanding of their dynamic characteristics. It is found that the fundamental frequencies of all the soldered leads are at least five times larger than those of the unsoldered leads. A laser Doppler vibrometer method is developed to measure the frequency of soldered and unsoldered leads of these four surface-mount components. Experiments and theory are in close agreement. The results presented should be useful for theoretically determining the reliability of solder joints under shock and vibration conditions, and for developing a solder joint inspection system for use in a controlled manufacturing process. >

The reliability of fine pitch solder joint interconnection has been studied. It consists of two different fine pitch surface mount components (SMCs), namely, the EIAJ (Electronic Industry Associates of Japan) 160-pin quad flat pack (QFP) and the JEDEC (Joint Electronic Device Engineering Council) 132-pin plastic quad flat pack (PQFP). Each has a lead-spacing (from lead-center to lead-center) of approximately 0.025 in. For comparison purposes the conventional JEDEC 68-pin plastic leaded chip carrier (PLCC) and the 84-pin PLCC have also been used in the same manufacturing process. The solder joint reliability of these four SMCs has been quantified for the mechanical shock, mechanical vibration, and thermal environmental stress factors. The results show that all the solder joints under consideration will survive 10 million cycles according to the general military practice. Reliability design charts for the solder joints of these assemblies have also been developed. From these charts, the reliability of solder joints at a given statistical confidence level can be estimated. >

The thermal stress response of YBa/sub 2/Cu/sub 3/O/sub 7-x/ superconducting microstrip lines on GaAs, Si, Al/sub 2/O/sub 3/, and MgO dielectric substrates has been studied using the finite-element method. Detailed stress distributions near critical areas of the systems were calculated to understand the mechanical behavior of the composite. The resulting stress fields are very high (large enough to cause cracking in the composite structure) for some of the dielectric materials due to the thermal expansion mismatch between the superconducting material and the dielectric substrate. YBa/sub 2/Cu/sub 3/O/sub 7-x/ superconducting microstrip lines on MgO displayed the best thermal-mechanical properties. It is concluded that the management of stresses resulting from the operating thermal environment will be a critical design constraint for the manufacture of reliable superconductor interconnects. >

Thermal stresses in surface-mounted small-outline integrated-circuit (SOIC) assemblies have been studied by the finite-element method. Emphasis is placed on the effects of solder-joint geometry on package and interconnection reliability. In addition, the problem of voids in solder joints is addressed. Seven different solder-joint geometries and six different sizes of voids are considered. It was found that the effect of voids in the solder joint is to increase the stresses acting on it. Furthermore, it is concluded that the results presented herein can provide guidelines for solder-joint inspection. >

The thermal stresses of molded plastic chip carriers (MPCCs) such as the plastic quad flat pack (PQFD) and plastic leaded chip carriers (PLCCs) are studied using the finite-element method. Two different types of lead frame materials are considered, alloy-42 and copper. The predicted failure mechanism agrees well with experimental data. In addition, a dual-inline package (DIP) with two different molded plastics is analyzed, and the stress results obtained by the finite-element method are found to be in excellent agreement with the experimental results. The results presented provide a better understanding of the thermal behavior of molded plastic packages and demonstrate the feasibility of using the finite-element method to design such electronic packaging. >

The thermal, mechanical and vibration responses of flip chip and PBGA (Plastic Ball Grid Array) solder joints have been determined in this study. The effects of overload environmental stress factors on the mechanical responses of the solder joints have been determined by bending and twisting experiments. The effects of shipping environmental stress factors on the vibration responses of the solder joints have been determined by out of plane vibration experiments. Also, the thermal fatigue behavior of solder joints have been investigated by nonlinear finite element, Coffin-Manson, and fracture mechanics methods.

The closed-form thermoelasticity solutions of electronic packages subjected to an instantaneous source of heat, and a heat source varying harmonically as function of time are presented. Useful curves and charts which relate the variables, time, frequency, heat, temperature, stress, displacement, and material property are also provided for engineering practice convenience. Also, the. Present results can be used to verify finite element analysis procedures and interpret experimental data.

The creep analysis of solder-bumped flip-chip on microvia build-up printed circuit board (PCB) with underfill encapsulant subjected to thermal cycling conditions are presented. Emphasis is placed on the effects of the conventional PCB's additional microvia build-up circuits on the solder joint reliability of the direct chip attach (DCA) assembly. The 62Sn-36Pb-2Ag solder joints are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint, and the von Mises stress and effective plastic strain in the microvia are presented for a better understanding of the thermal-mechanical behaviors of the solder bumped flip chip on build-up PCB with microvia circuits. It is found that, due to the very large thermal expansion mismatch among the silicon chip, solder joints, underfill encapsulant, build-up resin, electroplated copper microvia, and the FR-4 epoxy glass PCB, the stress and strain in the solder joints are higher than those of a DCA on a conventional PCB.

Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8") wafer by stencil printing method. These factors are: paste types (type 3 and type 4), squeeze forces (9 and 12 lbs.), snap-off heights (0 and 5 mils), aperture shapes (square and circle), and aspect ratios (2.5 and 2.75). They are varied to form a two-level L8 orthogonal array experiment. Analysis of mean (ANOM) and analysis of variance (ANOVA) are used to choose the most influential factors. After fixing the most influential factors, a two-level L4 orthogonal array experiment is followed to optimize the other material and process parameters. Important results are summarized in this paper which could be very useful for wafer bumping with stencil printing method.

A novel, simple processing and wafer level packaging method for a 4/spl times/4 Resonant Cavity LEDs chip with individual array is under development. Palladium/Gold (Pd/Au) alloys are used as p-type contacts and as rewiring metallization for optoelectronic devices to improve the fabrication process. By use of these alloys we have found a reduction of a factor of 10 in the resistance compared to Titanium/Gold (Ti/Au), due to the formation of a conducting oxide at the interface between the metal and semiconductor. On the packaging side, electroplated solder deposition was used to fabricate eutectic solderbump arrays on the chip. For the Under Bump Metallurgies (UBM), a thin layer (100 nm) of Ti and a layer (200 nm) of Cu was sputtered on the wafer. A 10 /spl mu/m thick copper stud is platted on top of the UBM to be used as a stem for the solder.

The author provides some guidance on submitting manuscripts to technical conferences and archival journals for publication. Emphasis is placed on the important items, strategy, and procedures for submitting manuscripts to IEEE (Institute of Electrical and Electronics Engineers) and IEE (Institution of Electrical Engineers) publications. >

This study deals with the determination of natural frequencies of a non-uniform cantilever beam which carries a concentrated mass at the free end. The effect of the rotary inertia of the end mass has been included. Numerical results for the first five eigenfrequencies are presented for a wide range of values of the beam dimensions and the concentrated mass.

The mechanical integrity of surface-mount technology (SMT) plastic leaded chip carrier (PLCC) solder joints has been studied by a four-point mechanical flexure fatigue test. The effects of printed circuit board (PCB) pad surface composition and testing temperature on solder-joint reliability are emphasized. Three sets of PCBs have been tested, one with Cu-Ni-Sn pad surface metallurgy, one with Cu-Ni-Au, and one with SMOBC/SSC (solder mask over bare copper selective solder coating). The solder composition was the 63 wt.%Sn/37 wt.%Pb eutectic. A two-parameter Weibull distribution was used for the lifetime model for these three products. The uniformity, quality, reliability, and a comparison of these products are discussed. The joints formed on Cu-Ni-Au and SMOBC boards were appreciably more reliable than those formed on the Cu-Ni-Sn board. >

The analytic description of thermal stresses and strains in surface mount chip carrier assemblies have been studied by a nonlinear finite element method. Emphasis is placed on the effects of packaging material and package size on interconnection and package reliability. In parallel, test boards with 68-Pin plastic leaded chip carriers (PLCC) have also been made and subjected to temperature cycling. The observed failure mechanism of the solder joints agreed with the finite element results.

A 12*12 stiffness matrix of the gull-wing lead and solder joint in a plastic quad flat pack (PQFP) surface-mount assembly was obtained by using a three-dimensional finite-element method. Deformation of the composite structure for each imposed unit displacement (or rotation) then obtained. The whole-field stress distributions in the gull-wing and solder joint provide a better understanding of their characteristics. The results presented herein can provide guidelines for the design of PQFP gull-wing leads and solder-joint reliability. >