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Abstract A wide reservoir computing system is an advanced architecture composed of multiple reservoir layers in parallel, which enables more complex and diverse internal dynamics for multiple time-series information processing. However, its hardware implementation has not yet been realized due to the lack of a high-performance physical reservoir and the complexity of fabricating multiple stacks. Here, we achieve a proof-of-principle demonstration of such hardware made of a multilayered three-dimensional stacked 3 × 10 × 10 tungsten oxide memristive crossbar array, with which we further realize a wide physical reservoir computing for efficient learning and forecasting of multiple time-series data. Because a three-layer structure allows the seamless and effective extraction of intricate three-dimensional local features produced by various temporal inputs, it can readily outperform two-dimensional based approaches extensively studied previously. Our demonstration paves the way for wide physical reservoir computing systems capable of efficiently processing multiple dynamic time-series information.

Abstract Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

We present a capacitor-free, scalable CMOS neuron circuit that offers significant benefits, including a compact circuit area, low power consumption, adjustable firing threshold, and scalability. This circuit generates output pulses with widths that increase in proportion to the input current magnitude. It also features an adjustable firing threshold (1-6 nA), indicating the minimum input current required to trigger an output pulse. Fabricated using standard 180 nm CMOS technology, the circuit occupies an area of $200~{\mu }$ m2 and consumes 1.4 pJ of energy per output pulse.

Abstract Memristors have attracted increasing attention due to their tremendous potential to accelerate data-centric computing systems. The dynamic reconfiguration of memristive devices in response to external electrical stimuli can provide highly desirable novel functionalities for computing applications when compared with conventional complementary-metal–oxide–semiconductor (CMOS)-based devices. Those most intensively studied and extensively reviewed memristors in the literature so far have been filamentary type memristors, which typically exhibit a relatively large variability from device to device and from switching cycle to cycle. On the other hand, filament-free switching memristors have shown a better uniformity and attractive dynamical properties, which can enable a variety of new computing paradigms but have rarely been reviewed. In this article, a wide range of filament-free switching memristors and their corresponding computing applications are reviewed. Various junction structures, switching properties, and switching principles of filament-free memristors are surveyed and discussed. Furthermore, we introduce recent advances in different computing schemes and their demonstrations based on non-filamentary memristors. This Review aims to present valuable insights and guidelines regarding the key computational primitives and implementations enabled by these filament-free switching memristors.

Despite the significant progress made in deep learning on digital computers, their energy consumption and computational speed still fall short of meeting the standards for brain-like computing. To address these limitations, reservoir computing (RC) has been gaining increasing attention across communities of electronic devices, computing systems, and machine learning, notably with its in-memory or in-sensor implementation on the hardware–software co-design. Hardware regarded, in-memory or in-sensor computers leverage emerging electronic and optoelectronic devices for data processing right where the data are stored or sensed. This technology dramatically reduces the energy consumption from frequent data transfers between sensing, storage, and computational units. Software regarded, RC enables real-time edge learning thanks to its brain-inspired dynamic system with massive training complexity reduction. From this perspective, we survey recent advancements in in-memory/in-sensor RC, including algorithm designs, material and device development, and downstream applications in classification and regression problems, and discuss challenges and opportunities ahead in this emerging field.

Abstract Interface‐type (IT) resistive switching (RS) memories are promising for next generation memory and computing technologies owing to the filament‐free switching, high on/off ratio, low power consumption, and low spatial variability. Although the switching mechanisms of memristors have been widely studied in filament‐type devices, they are largely unknown in IT memristors. In this work, using the simple Au/Nb:SrTiO3 (Nb:STO) as a model Schottky system, it is identified that protons from moisture are key element in determining the RS characteristics in IT memristors. The Au/Nb:STO devices show typical Schottky interface controlled current–voltage (I–V) curves with a large on/off ratio under ambient conditions. Surprisingly, in a controlled environment without protons/moisture, the large I–V hysteresis collapses with the disappearance of a high resistance state (HRS) and the Schottky barrier. Once the devices are re‐exposed to a humid environment, the typical large I–V hysteresis can be recovered within hours as the HRS and Schottky interface are restored. The RS mechanism in Au/Nb:STO is attributed to the Schottky barrier modulation by a proton assisted electron trapping and detrapping process. This work highlights the important role of protons/moisture in the RS properties of IT memristors and provides fundamental insight for switching mechanisms in metal oxides‐based memory devices.

In this work, the effect of rapid thermal annealing (RTA) temperature on the ferroelectric polarization in zirconium-doped hafnium oxide (HZO) was studied. To maximize remnant polarization (2Pr), in-plane tensile stress was induced by tungsten electrodes under optimal RTA temperatures. We observed an increase in 2Pr with RTA temperature, likely due to an increased proportion of the polar ferroelectric phase in HZO. The HZO capacitors annealed at 400°C did not exhibit any ferroelectric behavior, whereas the HZO capacitors annealed at 800°C became highly leaky and shorted for voltages above 1 V. On the other hand, annealing at 700 °C produced HZO capacitors with a record-high 2Pr of ∼ 64 μC cm−2 at a relatively high frequency of 111 kHz. These ferroelectric capacitors have also demonstrated impressive endurance and retention characteristics, which will greatly benefit neuromorphic computing applications.

Designing energy efficient systems capable to directly process signals at biological voltages remains a challenge. Here, the authors propose a bio-compatible memristor device based on protein-nanowire dielectric, harvested from the bacterium Geobactor sulfurreducens, working at biological voltages.

Though artificial sensory systems based on electronic devices have been realized, further transformation of data into spikes is required for neural network optimization. Here, based on NbO x Mott memristors, the authors report artificial spiking afferent nerves for accessing spiking systems and demonstrate spiking mechanoreceptor systems.

Sneak path current is a fundamental issue and a major roadblock to the wide application of memristor crossbar arrays. Traditional selectors such as transistors compromise the 2D scalability and 3D stack‐ability of the array, while emerging selectors with highly nonlinear current–voltage relations contradict the requirement of a linear current–voltage relation for efficient multiplication by directly using Ohm's law. Herein, the concept of a timing selector is proposed and demonstrated, which addresses the sneak path issue with a voltage‐dependent delay time of its transient switching behavior, while preserving a linear current–voltage relationship for computation. Crossbar arrays with silver‐based diffusive memristors as the timing selectors are built and the operation principle and operational windows are experimentally demonstrated. The timing selector enables large memristor crossbar arrays that can be used to solve large‐dimension real‐world problems in machine intelligence and neuromorphic computing.

As semiconductor technology enters the more than Moore era, there exists an apparent contradiction between the rapidly growing demands for data processing and the visible inefficiency rooted in traditional computing architecture. Neuromorphic systems hold great prospects in enabling a new generation of computing paradigm that can address this issue, which demands device components with rich dynamics and nonlinearity. Herein, the nonlinearity in memristive devices and their application in building neuromorphic dynamic systems are reviewed. The internal mechanisms that endow memristive devices with nonlinearity and rich dynamics are reviewed and subsequently the nonlinear spiking neurons that are implemented utilizing the physical processes in memristors are shown. Typical examples on neuromorphic dynamic systems based on nonlinear memristors are summarized, including memristive reservoir, memristive oscillatory neural network, and memristive chaotic computing. Finally, an outlook in the development of neuromorphic dynamic systems is given.

Memristor as the fourth basic element of electric circuits has drawn substantial attention for developing future computing technologies. Sun et al. report the progress and the challenges facing researchers on understanding memristive switching, and advocate continuous studies using a synergistic approach.

The data included in this article provides additional supplementary information on our recent publication describing “Inducing tunable switching behavior in a single memristor” [1]. Analyses of micro/nano-structural and compositional changes induced in a resistive oxide memory during resistive switching are carried out. Chromium doped strontium titanate based resistance change memories are fabricated in a capacitor-like metal-insulator-metal structure and subjected to different biasing conditions to set memory states. Transmission electron microscope based cross-sectional analyses of the memory devices in different memory states are collected and presented.

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd layers that could achieve a NL of 3 × 105, which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta2O5/Ru based memristor on top of the proposed selector.

Summary: Memristive devices share remarkable similarities to biological synapses, dendrites, and neurons at both the physical mechanism level and unit functionality level, making the memristive approach to neuromorphic computing a promising technology for future artificial intelligence. However, these similarities do not directly transfer to the success of efficient computation without device and algorithm co-designs and optimizations. Contemporary deep learning algorithms demand the memristive artificial synapses to ideally possess analog weighting and linear weight-update behavior, requiring substantial device-level and circuit-level optimization. Such co-design and optimization have been the main focus of memristive neuromorphic engineering, which often abandons the “non-ideal” behaviors of memristive devices, although many of them resemble what have been observed in biological components. Novel brain-inspired algorithms are being proposed to utilize such behaviors as unique features to further enhance the efficiency and intelligence of neuromorphic computing, which calls for collaborations among electrical engineers, computing scientists, and neuroscientists.

Though memristors can potentially emulate neuron and synapse functionality, useful signal energy is lost to Joule heating. Here, the authors demonstrate neuro-transistors with a pseudo-memcapacitive gate that actively process signals via energy-efficient capacitively-coupled neural networks.

Memristor-based neural networks hold promise for neuromorphic computing, yet large-scale experimental execution remains difficult. Here, Xia et al. create a multi-layer memristor neural network with in-situ machine learning and achieve competitive image classification accuracy on a standard dataset.

The development of humanoid robots with artificial intelligence calls for smart solutions for tactile sensing systems that respond to dynamic changes in the environment. Here, Yoon et al. emulate non-adaption and sensitization function of a nociceptor—a sensory neuron—using diffusive oxide-based memristors.

Memristors can switch between high and low electrical-resistance states, but the switching behaviour can be unpredictable. Here, the authors harness this unpredictability to develop a memristor-based true random number generator that uses the stochastic delay time of threshold switching

High-density information storage calls for the development of modern electronics with multiple stacking architectures that increase the complexity of three-dimensional interconnectivity. Here, Wu et al. build a stacked yet flexible artificial synapse network using layer-by-layer solution processing.

Memristors are key structural units of complex memory and computing systems, yet most currently available memristors are based on materials that are not compatible with silicon technology. Here, the authors demonstrate a CMOS-compatible, self-rectifying memristor and arrays entirely based on p-Si/SiO2/n-Si.

Oxide memristors exhibit noise in excess of 2–4 orders of magnitude above the baseline at quantized conductance states. Here, the authors measure anomalous electrical noise at these states in tantalum oxide memristors and relate it to thermally-activated atomic fluctuations by numerical simulations.

Metal–insulator–metal (MIM) structures based on titanium dioxide have demonstrated reversible and non-volatile resistance-switching behavior and have been identified with the concept of the memristor. Microphysical studies suggest that the development of sub-oxide phases in the material drives the resistance changes. The creation of these phases, however, has a number of negative effects such as requiring an elevated voltage, increasing the device-to-device variability, damaging the electrodes due to oxygen evolution, and ultimately limiting the device lifetime. In this work we show that the deliberate inclusion of a sub-oxide layer in the MIM structure maintains the favorable switching properties of the device, while eliminating many of the negative effects. Electrical and microphysical characterization of the resulting structures was performed, utilizing X-ray and electron spectroscopy and microscopy. In contrast to structures which are not engineered with a sub-oxide layer, we observed dramatically reduced microphysical changes after electrical operation.