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Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n/sup -/ region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n/sup +/ implant by sidewall spacers to suppress the n/sup +/-gate overlap to zero while keeping the n/sup -/ region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed. >

With the miniaturization of the diffusion process, the leak current per transistor tends to increase and the number of transistors per die tends to become larger, thus rendering more difficult the discrimination through the absolute value of IDDQ (quiescent power supply current) that is required to detect defects on VLSI (Very Large Scale Integration). While various statistical methods have been disclosed, this paper describes first the effects of an increase in the average value of IDDQ due to process dispersion on the IDDQ distribution and presents a theorization to estimate the defect detection rate of various IDDQ testing methods. Corroborative results will then show the validity of the presented theory on the defect detection rate of IDDQ.

With the miniaturization of the diffusion process, the leak current per transistor tends to increase and the number of transistors per die tends to become larger, thus rendering more difficult the discrimination through the absolute value of IDDQ (Quiescent power supply current) that is required to detect defects on VLSI (Very Large Scale Integration). On the other hand, scan patterns convenient for their logical quality improvement are widely used. When adopting such a scan pattern and measuring the IDDQ, one finds that the measured values do not fluctuate greatly. In this paper, we will present a method of determining good and defective dies by making an approximation of this distribution using a gamma distribution and we will demonstrate the efficiency of our method through corroborative results.

For functional failure analysis, use of the scan design for effective testing of sequential circuits is very popular and can be considered the norm for the LSI industry. However, in order to take advantage of the features offered by scan designs, it is imperative that the scan chain is operating properly. In this paper, I will introduce a new technique for the efficient diagnosis of the scan chain. The basis for this paper is that if a failure occurs in the scan chain, irregular IDDQ current flow will occur and identify the defective chain. Moreover, the actual location of the failure inside the chain can also be ascertained. Then, with result of exemplification, I shall prove the effectiveness of this method.

In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. In this paper, we will present a new method consisting of the automatic generation of a functional test pattern, formed by a combination of instructions sets and enabling the efficient improvement of the fault coverage. With this method, a test pattern is first generated to test all of an S number of instruction mnemonics. Then, for the faults that were undetected by that test pattern, an L number of sets of K number of instructions are drawn from the S number of instructions, and the set enabling the efficient improvement of the fault coverage is selected. By repeating this procedure, a high fault coverage can be obtained with a short test pattern. The effectiveness of our method was proved by the results of experiments obtained with the software that was created based on this method.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level. >

Recent advances in semiconductor production technology have enabled the on-chip configuration of integrated circuit systems. This has resulted in the increase of mixed signal LSIs that contain digital LSIs and analog LSIs, that have up till now been produced individually, being integrated on a single chip. When compared with individual digital and analog tests up till now, mixed signal LSIs pose the following problems for high-precision testing. High-precision measurement is difficult due to peripheral noise as analog signals are handled, and the reproducibility of measurement results is poor. This paper describes a method of testing sigma-delta D/A converters and LCD driver LSIs using an example where the above problems in a mixed signal LSI were solved. When conducting high-precision measurement of sigma-delta D/A converters with a mixed signal tester, measurement at the same precision as when a high-precision tester is used is possible when the influence of clock jitter, the influence of the power supply, the influence of peripheral circuits, and the dynamic range of the measurement system are taken into consideration. With respect to LCD driver LSIs, this paper describes testing problems and two inspection methods, the differential comparator system and the digitizer system. >

Gate-capacitance characteristics for LATID (large-angle-tilt implanted drain) devices are studied using high-resolution measurements and device simulation. As compared with single-S/D (source/drain), a deep-submicron LATID FET, developed to introduce sidewall spacers for reducing overlap length to approximately 0.09 mu m, is found to suppress gate-to-drain capacitance C/sub GD/ at 3.3 V operation by approximately 40%, to almost the same level as LDDs (lightly doped drains), while a LATID without spacers suffers from a >25% larger C/sub GD/. To suppress C/sub GD/, offsetting the n/sup +/ region by spacers is crucial, while the n/sup -/ region should remain fully overlapped with the gate to improve current drivability. Following this design guideline, the circuit speed of LATID can be improved by approximately 15% compared to LDDs. The deep-submicron LATID technology, with spacers, is promising for high-speed ULSI circuits. >

In recent years, coupled with the lower voltages, lower power and current consumption and higher speeds brought about by miniaturization, VLSI has been experiencing radical changes in technology such as an increase in scale, higher integration and an increase in the number and complexity of functions. In spite of these technological changes, reduction of manufacturing costs is still a major task at the VLSI manufacturing site. This paper will study the maximum limit of the chip area enabling the manufacture of cheap VLSI and will show that when developing and manufacturing devices having a chip area that exceeds this limit it is more advantageous to use two-chip, three-chip, or multi-chip devices.

The most important points concerning the manufacturing test of VLSI are (1) High quality testing, (2) Low cost testing procedures and (3) Fast development. However, together with the high integration of VLSI, recent large-scale, multi-functional and complex technology has made the above test procedures more and more difficult to secure. Especially in regard to measurement quality, where stable measurement is performed at the factory, and the testing results quality, which prevents faulty devices from being shipped once test is completed, the actual level of technology does not provide a complete solution for the initial stage of the introduction at the factory even through the implementation of a large number of procedures. This paper will study the reduction in the defect level in order to improve the quality of microprocessors through the addition of new methods ("flag check" and "address check") to the conventional Single Stuck-at Fault verification.

The most important points concerning the manufacturing testing of VLSI are (1) The guaranteed high quality of the testing itself, (2) Low cost testing procedures and (3) Fast development and operation. However, together with the high integration of VLSI, recent large-scale, multi-functional and complex technology has made the above testing procedures more and more difficult to secure. Our section is in charge of the establishment of the manufacturing testing procedures for all MOS-VLSI, excluding stand-alone MOS memory, and of the management of the technological data of all tests. In this paper, we will analyze this data and disclose the results of our study concerning testing costs. In particular, we will discuss the actual necessity of introducing test circuits in regard to the testing costs, and how to obtain the appropriate value for such circuits.

The introduction of low-priced test systems and the reduction of the test time are necessary in order to decrease the testing costs that are included in the cost of manufacturing VLSI. However, coupled with the miniaturization of the fabrication process, the test time tends to become considerably longer for multifunctional and complex VLSI with high integration. In this paper, we present a new method enabling the automatic reduction of the test time. This method consists of shortening the test time by installing virtual tester hardware on the tester CPU memory in order to delete duplicate tester hardware setting instructions. The efficiency of this method is proven by experiments showing that a test time reduction of 5/spl sim/25% could be obtained.

A topic of great concern in VLSI manufacture is yield. One way to improve practical yield is to design redundant memory or logic circuits and switch over to this redundant circuit if fault occurs in the principle memory or main logic circuit. This paper reports the repairing ratio of no good devices on the main circuit and how large of a redundancy-repairing circuit would be economically feasible.

In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. This paper discusses how fault coverage can be improved with a short test pattern that repeatedly samples an R number of instructions as L sets from an S number of instructions and selects from amongst these L sets those for which the fault coverage can be improved. Continuing, it argues that the processing speed can be increased by selecting a certain number of sets containing an R number of instructions from an S number of instructions. This approach proved effective in tests using software created on these principles.