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The challenge for the upcoming full-chip CD uniformity (CDU) control at 32nm and 22nm nodes is unprecedented with expected specifications never before attempted in semiconductor manufacturing. To achieve these requirements, OPC models not only must be accurate for full-chip process window characterization for fine-tuning and matching of the existing processes and exposure tools, but also be trust-worthy and predictive to enable processes to be developed in advance of next-generation photomasks, exposure tools, and resists. This new OPC requirement extends beyond the intended application scope for behavior-lumped models. Instead, separable OPC models are better suited, such that each model stage represents the physics and chemistry more completely in order to maintain reliable prediction accuracy. The resist, imaging tool, and mask models must each stand independently, allowing existing resist and mask models to be combined with new optics models based on exposure settings other than the one calibrated previously. In this paper, we assess multiple sets of experimental data that demonstrate the ability of the Tachyon TM FEM (focus and exposure modeling) to separate the modeling of mask, optics, and resists. We examine the predictability improvements of using 3D mask models to replace thin mask model and the use of measured illumination source versus top-hat types. Our experimental wafer printing results show that OPC models calibrated in FEM to one optical setting can be extrapolated to different optical settings, with prediction accuracy commensurate with the calibration accuracy. We see up to 45% improvement with the measured illumination source, and up to 30% improvement with 3D mask. Additionally, we observe evidence of thin mask resist models that are compensating for 3D mask effect in our wafer data by as much as 60%.

While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today's full-chip CDU specifications are already pushing physical limits at extreme lithography k 1 factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency. In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and "safe" ambit radius for assuring accurate CD prediction. Selections of image pixel size and "safe" ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore's Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.

Model based optical proximity correction (OPC) today has become a necessity in advanced lithography for 65nm and 45nm design rules in order to achieve production-worthy pattern fidelity. The typical practice is to use a limited set of test structures to calibrate and determine the OPC model parameters. The guide for the selection of test structures for OPC model calibration has been mainly relied on experience and physical intuition. To date, there is no known quantification methodology to ensure that the calibrated model from a limited set of test structures can reliably "cover" a full-chip OPC application without any ambiguity under a known set of design rule constraints. Doubts from this ambiguity demand an extra design for manufacturing (DFM) verification step in addition to the already lengthy OPC application process. This is since semiconductor manufacturing requires that the post-OPC mask data contains no errors, or at least no catastrophic errors induced by OPC treatment, e.g., bridging or short. However, such DFM verification tools are again based on a perilous assumption that either one can use the same or yet another "calibrated" model from a limited set of test structures to check the OPC treated full-chip data for all possible trouble spots. In reality, a "calibrated" model may never be able to apply adequately to those of random two-dimensional (2-D) pattern structures on a full-chip that are lithographically unrelated to the limited set of test structures used for the model calibration. To ensure a more comprehensive coverage of the OPC model, we need a methodology that can quantify generalized 2-D test structures suitable for model calibration. In this paper, we propose a method to quantify generalized, 2-D patterns by representing them in "imaging signal space". The method that translates geometrical design rules into the boundary in "imaging signal space" is elaborated. We propose several critical quantities to characterize OPC model on a quantitative foundation to assess model from a statistical point of view.

Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k1 imaging factor for each patterning step. With combined patterns, we can achieve overall k1 factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or one-sixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process. In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks. To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.

Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k 1 conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k 1 250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

factors around 0.3. Double dipole lithography (DDL) is becoming a popular RET candidate for foundries and memory makers to pattern the poly gate active layer [2, 3, 4]. Double exposure method or double pattern technique (DPT), [5, 6, 7] using ternary 6% attenuated PSM (attPSM) is a good imaging solution that can reach and likely go beyond the 45nm node. In this work, back end of the line (BEO L) metal like test structures were used for developing a model-based dark field DDL method. We share our findings of using DDL for patterning 45nm node trench structures with binary intensity mask (BIM) on a dry high NA ArF scanner. Key words: double exposure technique, DET, Double Dipole Lithography, DDL, Double Pattering, Model based layout conversion, Dark field, trench patterning. 1. INTRODUCTION Clear field DDL with immersion and polarization is a good RET solution for printing the poly gate layer. The main advantages of the clear field DDL technique are that it [5]: 1. resolves the scalability and printability problem for scattering bars (SB) or assist features (AF); 2. allows printing devices using high contrast dipole illumination; and 3. enables to apply linear polarization for patterning device structures based on model based layout conversion method. The ITRS roadmap uses the metal1 pitch as one of the fundamental measures for successive device generations (Table 1). This is because the metal pitch defines the dens ity of integration and is therefore the dimension that is driven the hardest from a pitch shrinking perspective. Presently the back end metal interconnects processing all utilizes a low-k dielectric with copper damascene integrati on scheme that requires printing small dimension trenches at very tight pitches. Due to the inherent high contrast for dipole illumination, it is a good illumination choice for imaging dense trench. Figure 1 shows the simulated normalized image log slope (NILS=CD*ILS) NILS for 45nm half pitch where mask CD varies from 45 to 100nm under versus different k

For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RET's beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k 1 for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

The contact hole imaging is a very challenge task for the optical lithography process during IC manufacturing. Lots of RETs were proposed to improve the contrast of small opening hole. Scattering Bar (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 contact imaging. In this study, an effective model-based SB OPC based on IML technology is implemented for contact layer at 90nm, 65nm, and 45nm nodes. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. Then, we selected the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, the model-based SB OPC is performed. Next, model OPC can be applied with the presence of SB for the entire chip. It is important to note that, for patterning at k1 near 0.35 or below, it may be necessary to include 3D mask effects with a high NA OPC model. With enhanced DOF by IML and immersion process, the low k1 production worthy contact process is feasible.

The technical challenges in using F2 lithography for the 45nm node, along with the insurmountable difficulties in EUV lithography, has driven the semiconductor chipmaker into the low k 1 lithography era under the pressure of ever decreasing feature sizes. Extending lithography towards lower k 1 puts heavy demand on the resolution enhancement technique (RET), exposure tool, and the need for litho friendly design. Hyper numerical aperture (NA) exposure tools, immersion [1], and double exposure techniques (DET's) are the promising methods to extend lithography manufacturing to the 45nm node at k 1 factors below 0.3. Scattering bars (SB's) [2] have become an integral part of the lithography process as chipmakers move to production at ever lower k 1 factors. To achieve better critical dimension (CD) control, polarization is applied to enhance the image contrast in the preferential imaging orientation, which increases the risk of SB printability. The optimum SB width is approximately (0.20 ∼ 0.25)*(λ/NA). [1] When the SB width becomes less than the exposure wavelength on the 4X mask, Kirchhoffs scalar theory under predicts the SB intensity. The optical weighting factor of the SB increases (Figure 1b) and the SB's become more susceptible to printing. Meanwhile, under hyper NA condition's, the effectiveness of sub-resolution SB's is significantly diminished. A full-sized scattering bars (FSB) scheme becomes necessary. Double exposure methods, such as using ternary 6% attenuated PSM (attPSM) for DDL, are good imaging solutions that can reach and likely go beyond the 45nm node. Today DDL, using binary chrome masks, is capable of printing 65 nm device patterns. [3, 4, 5] In this work, we investigate the use of DET with 6% attPSM masks to target 45nm node device. The SB scalability and printability issues can be taken cared of by using mutual trimming, i.e., with the combined energy from the two exposures. In this study, we share our findings of using DET to pattern a 45nm node device design with polarization and immersion. We also explore other double patterning methods which in addition to having two exposures, incorporates double coat/developing/etch processing to break the 0.25 k 1 barrier.

Low k1 lithography process enables the production of 90nm and 65nm nodes by introducing advanced resolution enhancement technology (RET) mask with complex layout. To ensure the printed wafer outcome that meets the original IC design specifications, we need to consider the manufacturability and to verify it during design stage. This means that we need to characterize the process capabilities and use them as the input parameters to examine the upcoming design via simulation verification before mask making. For those of potentially weak or marginal layout design areas identified during the checking stage, we need to build a robust algorithm to improve the RET mask treatment process or to modify the design layout when necessary. This is the basic concept for Manufacturing Reliability Check & Correction (MRC2). In our implementation, MRC2 carries the wafer manufacturability information. By performing MRC2 during the design phase, we can better achieve the goal of Design for Manufacturing (DFM). In this paper, we present two example cases for a production worthy MRC2 - CPL (with two mask writing steps) and DDL (with two exposure masks). From our viewpoints, the first checking step needs to single out the "weak printing spots" or to map out the treated CPL/DDL features with unacceptable DOF and marginal exposure latitude. This allows using corrective actions to ensure a well-behaved printing of the entire chip during manufacturing. We recommend applying both MRC2 and electrical verification in the design verification loop iteratively until circuit performance prediction becomes satisfactory. The looping process generates useful feedback that adds to the RET knowledge database; hence, a more efficient DFM procedure.

The recent introduction of chromeless-phase lithography (CPL) has provided lithographers with a powerful wavefrontengineering tool for patterning at k 1 values below 0.3. Reliable image formation at such extreme k 1 requires a well-characterized CPL photomask. However, the limitations of available optical inspection tools have made the test andmeasurement of CPL photomasks a difficult task. In this paper, we describe preliminary imaging and phase metrologyresults on a leading-edge CPL reticle using an high-resolution 193-nm microscope. This microscope features a solid-state 5-kHz repetition rate, 193.4 nm actinic light source in conjunction with high-numerical-aperture (0.75 NA) optics toprovide 200X magnification, 150-nm Rayleigh resolution and 35-nm pixel size over a 30-micron image field. Arecently-developed phase metrology architecture facilitates optical path difference (OPD) measurements of isolated ordense features on a sub-200-nm spatial scale. We discuss the phase measurement process and present images andcorresponding OPD measurements of line and contact structures on an ArF CPL reticle that is designed mainly for the 65nm technology node. We compare these OPD measurements with predictions based on surface nano-profilometer (SNP)step-height measurements of the same feature regions.Keywords : phase metrology, CPL, actinic, ArF, photomask, phase shift mask

We describe a new resist model calibration procedure and its implementation in LithoCruiser TM . In addition to the resist calibration, LithoCruiser is used to perform simultaneous optimization for numerical aperture (NA), mask OPC, and illumination profile with built-in manufacturing constraints for ASML illumination diffractive optical elements (DOE). This calibration procedure uses a global optimization algorithm for resist parameter tuning, matching the simulated and measured 2D resist contours at a user-defined multiple CD sampling across the selected developed 2D resist patterns. Using lumped parameter type resist models and vector high-NA simulation engine, this resist calibration procedure showed an excellent calibration capability of max CD error range < ±4nm for the CPL 70nm DRAM patterns. Calibration results for CPL 130nm contact hole patterns are also included in this manuscript. Dependency of the calibrated model parameters on lithography process (i.e., Quasar, C-Quad illumination and at different defocus) and further improvements to a more predictable resist model are discussed.

For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k 1 for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k 1 values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k 1 , it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPL TM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IML TM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RET's including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable the low k1 optical lithography. To meet the challenges imposed by the previously unthinkable low k1 for manufacturing with most stringent dimension control requirements, a capable OPC model to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new OPC model must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, usch as customer designed illuminator and experimental measured illuminator profile from the scanners. The physical and mathematical foundation of the model must be well thought of to meet the requirements for the above-mentioned applications. We have extended our Eigen Decomposition Model (EDM) for model OPC treatment into the high NA regime, in which the vector characteristics of light and thin film stack are taken into account. For CPL calibration, it has been found that 3D mask topography effect cannot be ignored in order to achieve satisfactory model accuracy.

Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm 1 . Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.

The theory of interference mapping lithography (IML) is presented for low k1 (k1

Chromeless-Phase Lithography (CPL) combined with IML (Interference Mapping Lithography) technology is experimentally demonstrated as a viable resolution enhancement technique (RET) to pattern low-k1 (0.39) contact holes (CHs) from dense through sparse pitches. Both the process latitude and the MEEF values are measured. The most promising single exposure techniques combine off-axis-illumination (OAI) with the use of non-printing assist features, as in the case of CPL with IML. Contrary to other RETs, CPL does not use sub-resolution assist features but non-printing assist slots with a well-chosen phase (180° or 0°) and transmission (0% or 100%) assignment. The optimization and the positioning of assist features result of IML, based on a mapping of the field intensity at the wafer level: the assist features interfere to enhance the image at the contact hole location. The experimental layout optimization is discussed, showing how the process is maximized together with the dose-margin before any side-lobe printing. Using ArF immersion lithography at 0.75 NA with Quasar 20° σout=0.92 / σin=0.72, the CPL printing performance of 100 nm contact holes, from 200 nm pitch through isolated, is measured. The Depth-Of-Focus at 8% Exposure Latitude (DOF @ 8% EL) remains above 0.4 μm through pitch, with 0.43 μm DOF @ 8% EL at the difficult 300 nm pitch. The MEEF becomes a multi-dimensional metric on CPL masks. The wafer CD uniformity depends not only on the size variation of the CH on the reticle, but also on the size variations at the two reticle write steps, i.e. the assist slots opening and the Cr removal. The MEEF metrics related to the CH and slot sizes appear as the most critical ones. For each of those parameters, measured MEEF is always below 3.

Double Dipole Lithography (DDL) has been demonstrated to be capable of imaging complex 2D patterns for full-chip application. Due to inherently high aerial image contrast, we have found that there is strong potential for this technology to meet manufacturing line width roughness (LWR) and critical dimension uniformity (CDU) requirements for the 65nm node using ArF binary chrome masks or 6% attenuated phase shift mask (AttPSM). For patterning at k1 less than 0.35, DDL is a Resolution Enhancement Technology (RET) that offers an acceptable process window without resorting to costly hard phase shift masks. To use DDL for printing actual IC device patterns, the original design data must be converted into “vertical (V)” and “horizontal (H)” masks for the respective X and Y dipole exposures. An improved model-based DDL mask data processing steps has been demonstrated that it is possible to convert complex logic and memory data to X-Y dipole exposure compatible layout. Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of chrome in open field areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for most poly gate masks using a positive resist process. In this work, we report an improved model based DDL layout conversion methodology for full-chip application. A new generation of DDL technology reticle set was developed to verify the performance. Background light shielding is a critical part of the DDL. We report an innovative shielding scheme to minimize the negative impact of stray light for the critical features during double exposures.

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable optical lithography tackling 45nm node and beyond. To meet the challenges imposed by the previously unthinkable low k 1 for manufacturing with most stringent dimension control requirements, a capable model OPC to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new model OPC must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, such as customer designed illuminator and experimental measured illuminator profile from the scanners. This capability is very important since the real illuminator pupil can impact OPC accuracy. The physical and mathematical foundation of the model must be well thought of to meet the requirement for the above-mentioned applications. We have developed a novel Eigen Decomposition Model (EDM) for model OPC treatment applicable for all types of advanced binary and phase-shifting masks. Together with a full 2D model calibration and verification methodology, the results from this new model OPC have proven to achieve a superb CD accuracy with versatile capabilities for extreme low k 1 imaging application. This report will explain how the model works with example applications and actual wafer results.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k 1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k 1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.

Under low-k 1 patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k 1 imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k 1 factor for the three types of circuits. For 90nm node with k 1 as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.

The chromeless phase lithography is a potential technology for low k1 optical image. Since the image quality is controlled by the phase interference, the phase error that results from mask processing becomes an issue. In the previous study, we have investigated the phase error effect and optimized the etching recipe by using the orthogonal DOE method. However, the 3D pattern profile is another critical factor, which affect the image intensity and needs to be clarified. In this paper, the through pitch L/S pattern with various profile angles were studied. Test patterns were measured, and verified by AFM, SEM, and metrology tools to get profile angles, phase values, and CD dimension. Simulation was used to predict the trend of process performance and analyze the impact on process control. The process windows for specific pattern profiles were also verified by wafer printing result. An optimized etching process and a set of spec recommendations for the CPL PSM was obtained.

Resolution Enhancement Techniques (RET), or low k1 imaging, has been deployed successfully to extend the resolution limits of optical lithography significantly below half-λ for today's poly gate mask in the state-of-the-art manufacturing processes. However, achieving satisfactory contact hole patterning through the full pitch range required for the 90nm and 65nm technology nodes has greatly challenged the leading process development effort. Currently, attenuated PSM's with transmission between 5% and 9% are used to enhance the resolution of dark field contact hole patterns. Using conventional illumination with a low sigma, which is the common method employed for att-PSM, limits the minimum pitch that can be resolved on the wafer. By using off-axis illumination (OAI) it is possible to image smaller pitches. However, the same attributes that enhance imaging for dense patterns severely degrade the imaging of isolated patterns. Using Chromeless Phase Lithography (CPL), sub-wavelength isolated contact patterns can be imaged using strong off-axis illumination, such as Quasar, dipole and double dipole, etc. By applying modeled sub-resolution and non-printing features, we found it is possible to achieve very high-resolution contact imaging with exceptional process latitude. Both phase shifted and non-phase shifted patterns can be much larger than sub-resolution assist features (or anti-Scattering Bars) used on dark field binary reticles (~three times larger), making the reticle pattern easier to manufacture. Using this method, sub-wavelength bright patterns on a dark field can be imaged through the full pitch range. We have shown that it is feasible to push the contact resolution limit to 0.33 k1 or smaller.

High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.

As IC fabrication processes are maturing for the 130nm node, silicon manufacturers are focusing on 90nm device manufacturing at ever-lower k 1 factors. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at similar k 1 near 0.3. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique. For low-volume, the high mask cost of Alt-PSM discourages its use. What are the most sensible KrF lithography patterning options at k 1 = 0.3? For single exposure mask solutions at the 90nm node using KrF, there are two leading candidates: 6% attenuated PSM (Att-PSM) and Chromeless Phase Lithography (CPL). In this work, we explored and compared these two options in terms of the best achievable process latitude for patterning poly gate layer. First, we analyzed the diffraction patterns from 6% Att-PSM and CPL mask features and identified the optimum transmission for various pitches. Next, we examined the two options from a mask making perspective, accessing mask manufacturability, phase and transmission error control, defect sources, etc. In this paper, we describe how hybrid CPL can be used as a variable transmission mask to produce the best through pitch imaging performance and a practical implementation method for mask manufacturing.

From 90nm node and beyond, all of the advanced silicon wafer manufacturing processes are likely to heavily depend on the use of PSM. Two styles of PSM have been considered favorably for both 90nm and 65nm nodes, one is the 6% attenuated PSM and the other one is Chromeless Phase Lithography (CPL) mask. At 65nm node, both of the MoSi-based attenuated PSM and CPL mask are required to be etched into quartz substrate to achieve the desired pi-phase shift. In addition to the demand for very tight top-down mask CD control, for dry-etched process, there are two critical factors can have a significant impact to wafer CD control. They are the etch depth control through feature pitch and the overall etch slope profile. Both contribute to the phase variation. The phase variation degrades the overlapped process window and sufficient phase error can act like spherical lens aberration. This will no doubt impact the wafer imaging performance. In this work, we characterize our dry-etch process by using an orthogonal experiment method and then examine the performance of the optimized recipe by CD metrology, phase uniformity, and actual wafer printing result.

Double Dipole Lithography (DDL ¥ ) has been demonstrated to be capable of patterning complex 2D patterns [1]. Due to inherently high aerial imaging contrast, especially for dense features, we have found that it has a very good potential to meet manufacturing requirements for the 65nm node using ArF binary chrome masks. For patterning in the k 1 < 0.35 regime without resorting to hard phase-shift masks (PSMs), DDL is one unique Resolution Enhancement Technique (RET) which can achieve an acceptable process window. To utilize DDL for printing actual IC devices, the original design data must be decomposed into “vertical (V)” and “horizontal (H)” masks for the respective X- and Y-dipole exposures. An improved two-pass, model-based, DDL mask data processing methodology has been established. It is capable of simultaneously converting complex logic and memory mask patterns into DDL compatible mask layout. To maximize the overlapped process window area, we have previously shown that the pattern-shielding algorithm must be intelligently applied together with both Scattering Bars (SBs) and model-based OPC (MOPC)[1]. Due to double exposures, stray light must be well-controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of solid chrome in open areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for a typical clear-field poly gate masks to be patterned by a positive resist process. In this work, we report a production-worthy DDL mask pattern decomposition scheme for full-chip application. A new generation of DDL technology reticle set has been developed to verify the printing performance. Shielding is a critical part of the DDL. An innovative shielding scheme has been developed to protect the critical features and minimize the impact of stray light during double exposure. Keywords: double dipole lithography, DDL, DDL mask decomposition, scattering bars, SB, model OPC, pattern shielding, resolution enhancement technique, RET, overlay

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

CDU is probably one of the most important process control parameters for poly gate printing process. As the design rule has been shrunk to below 100nm node and k1 approaching 0.35, the required specifications for CDU are more stringently tightened. For low k1 lithogrpahy, optical proximity effect can severely impact CDU of the cirtical features from different neighboring environments, such as, isolated versus dense regions, or near the crowded corners and intersections, etc. Conventional model OPC has been assumed to correct mask feature CD at a best process setting condition. The approach has been widely adopted but it is increasingly becoming less satisfactory since this method does not take into account the process variation within the acceptable process window. In ASMLs LithoCruiser, for a selected CD cut-line, we use a Monte Carlo approach to randomly generate process conditions within the process window to simulate thousands of CDs. Based on the predicted CD distribution, we can calculate the predicted CDU Yield within the process window. Using LithoCruiser's Application Programming Interface (API) we can set up an optimization loop to adjust mask feature snippets for a desired imaging and process condition to achieve user specified CDU yield. Depending on the neighboring environment, mask snippets with the same target CD may need different biases and so are the features with different target CDs due to different degrees of optical proximity effects.

Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.

The application of Chromeless Phase Lithography, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k 1 ). As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k 1 semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time. CPL technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed.

Chromeless phase lithography (CPL) has been shown as a viable technology for 65nm technology node. Unlike alternating PSM, the CPL aerial image is formed by the interference from a pair of symmetrical phase edges. It is thus less vulnerable to mask phase errors and to the mask defect types that are otherwise highly sensitive to asymmetrical phase imaging. Among the various types of mask defects, the quartz bump has been singled out as the phase defects that must be captured and repaired during the CPL mask manufacturing 1 . In this paper, we focus on the CPL mask inspection and repair technologies for the quartz bump defect. Using a set of programmed CPL mask defects, we characterize the quartz defect inspectablity and repair capability. We then use AFM and SEM tools to scan the defect for the precise location and dimension. The FIB induced etching process, gas assist etching (GAE), are used for the quartz bump repair. In order to better control the repairing effect, a multi-pass GAE process was proposed. The defect repair performances were verified by AIMS and resist printing. We show that the quartz bump can be detected using the current state-of-the-art mask inspection tool and most importantly, it can be repaired effectively with minimum or little impact to the printing performance. Key words: Phase shifting mask, PSM, CPL, AFM, SEM, FIB, GAE

Chromeless phase Lithography (CPL) has been shown to be one of the promising low k1 technologies having the potential to extend optical lithography to nodes well beyond 100nm. A CPL mask can be either the mesa type phase shift mask for which the feature regions are protected during quartz etching, or the trench type phase shift mask for which the feature regions are etched away during quartz etching. It is conceivable that the photolithography performance could be different from these two different types of phase shift masks. In our rigorous electromagnetic field (EMF) simulations, we have observed that the light propagation behavior through the 3D mask features is very different for the two mask types, which causes the aerial image difference subsequently. The through pitch performance from rigorous EMF simulations shows that trench type CPL mask is a slightly better choice from the photolithographic performance point of view, under the illumination condition investigated here. It should be understood, however, that such a conclusion may not be generalized to other illumination conditions without further investigations. The observed zero MEEF zones in CPL technology impose great challenges to model OPC implementation that depends on aerial image characteristics, it can, however, be overcome by using other implementations.

Chromeless phase lithography (CPL, or previously named CLM) is based on using 100 percent transmission PSM in the critical patterning area. However, unlike the conventional single chromeless phase edge type, CPL forms pattern images based on a pair of symmetrical phase-edges in proximity. In principle, the mask pattern layout is very similar to attenuated phase shift mask. There is no need to be concerned with neither phase assignment nor phase conflict. The mask layout complexity is greatly reduced as compared to the requirement for alternating PSM. In this report, we discuss how to optimize CPL mask design for a full-chip application. One effective method is by applying chrome patches or 'chrome shields' on top of the optically sensitive pattern areas. In 'large' 100 percent phase transmission areas, the chrome shield can prevent printing an undesirable pattern. As for the 'critical' pattern areas, chrome shields can be effectively used for controlling optical proximity effects in order to enhance the printing performance. We found chrome scattering bar (SB) OPC is necessary to improve process window. Using LithoCruiser simulation, we predict that it is possible to obtain manufacturable overlapped-process-window across a full range of feature pitch for 70nm line CD target with ArF exposure.

Chromeless Phase Lithography (CPL) with a high NA exposure tool is shown to be an attractive technology solution for the 65nm node. Under strong image enhancement conditions, the traditional definition of minimum defect printability specifications is no longer adequate. This paper investigates defect printability issues for CPL technology. Based on optimized scattering bar OPC treatments through pitch, a set of defect printability quantification (DPQ) patterns was designed. In the DPQ design, a number of defect types have been programmed with progressively increasing defect size from 0.05(l/NA) to 0.3(l/NA). Each defect type and size on the actual CPL reticle were then fully characterized using an advanced CD SEM metrology system, the KLA8450RT with both wafer and reticle capabilities. This is a very critical step for quantifying defect printability, since in order to accurately assess the printability, the defect dimension must be well correlated to the original DPQ design on the reticle. The DPQ reticle was then printed using a high numerical aperture (NA) scanner (ASML /850T) so that it is possible to characterize the defect printability for each of the programmed defects and the impact on CD through pitch. Minimum printable defect (MPD), maximum non-printable defect (MNPD), and critical dimension (CD) variation percentage were used as metrics to characterize the critical defect size and the sensitivity of each defect type. The purpose of this study is to understand the tolerance of the CLM technology to printable defects and establish a realistic and sensible defect specification.

The extension of KrF lithography has become the major trend in semiconductor manufacturing due to the delay of ArF lithography. Therefore, various resolution enhancement techniques (RETS) are employed for sub 100nm node patterning. This paper introduces the 100 percent transmission PSM as a candidate for resolving the problems with previous approaches using a transparent phase-shift mask. CLM shows a high optical performance and relatively simple mask fabrication compare to other strong phase-shift mask. However, full-chip level CLM application is still under development due to the difficulty of mask manufacturing and lack of proper layout converting environment. In this paper, we covered mask-making process such as the quartz dry etch and defect engineering which are critical to CLM manufacturing. We made a test mask based on the basic CLM concept and evaluated its optical performance. Finally, we will show the feasibility of chrome-less mask manufacturing for real device application.

The Chromeless Phase Shift Mask (CLM) approach from ASML MaskTools has been developed as an approach to achieve sub-100nm lithography using currently available stepper technology. The technology uses sub-resolution gray-scaled regions of zero-phase and pi-phase quartz on the mask to produce effective feature widths well below 100nm at the wafer. The features on the mask consist entirely of etched and unetched quartz. No features consist of chrome on the mask. The integration of this type of phase shift mask technology into the photomask-manufacturing environment requires that the mask manufacturer be able to inspect the mask for defects in the quartz. The Defect Sensitivity Monitor (DSM) pattern was used to construct a CLM mask. The mask was inspected using commercially available inspection platforms, and the resulting inspection capability is reported.

We have developed an ultrafast lithographic 2D aerial image simulator named LithoCruiser TM . It employs a novel algorithm based on Hopkins imaging (Titanium model). Compared to currently available simulation tools, LithoCruiser has demonstrated an order of magnitude increase in computational speed. This makes it well suited for predicting the printing of sizeable 2D patterns as well as the analysis of overlapping process windows for multiple feature cut-lines. With such a high computational speed, there is a need to determine whether its accuracy has been compromised. A comprehensive set of comparisons was performed against an internal standard based on Abbe imaging (Platinum model) - one that is comparable to commercially available simulators. Analyses of CD through pitch for three 1D mask types (binary chrome, dark field, and PSM) as a function of NA, illumination, and aberrations were conducted. LithoCruiser predicted trends through pitch that agreed well with both internal standard and commercially available lithography simulators. Largest deviations were no more than 5 to 10 nm with typical values of 3 to 5 nm. As the LithoCruiser accuracy setting was increased, CD values converged to target values. The accuracy of CD values was essentially independent of simulation grid setting when less than or equal to 10 nm.

In this paper the concept of chromeless phase lithography (CPL) is introduced and experimental results on an ASML PAS 5500/800 are presented. CPL is a single exposure technique and is capable of resolution enhancement on all device layers (bright and dark field masks). Line space structures through pitch are measured with cross section and have O.35jim depth of focus (DOF) at 10% exposure latitude without forbidden pitches. CPL experimental results for a k1 of 0.38 (½ pitch) are presented for three DRAM device layers, isolation brick wall, storage capacitor, and honeycomb contact. Each of these layers have a DOF of O.35jim at 10% exposure latitude. CPL experimental results are presented for a SRAM gate and contact with lOOnm feature size (k1=O.32) and have a DOF of O.35jim at 10% exposure latitude.

Due to delays in the development of next generation lithography (NGL), extension of optical lithography has become the major trend in semiconductor manufacturing. As a result, various resolution enhancement techniques (RET's) are under development, especially for sub-100 nm node patterning. This paper introduces a concept of 100% transmission PSM (Chrome-Less Mask: CLM) for resolving some problems associated with previous approaches that used transparent phase-shift mask. This CLM technology has advantages for simple fabrication and high performance due to its improved resolution limit. However, owing to limited mask manufacturability and lack of proper techniques for converting the layout coupled with required illumination conditions, CLM application in real device is still in the development stage. Proper mask making technology in particular is a major issue. In this paper, we cover mask- making process, especially the quartz dry etch and defect engineering. With this mask-making technology, we made a test mask and evaluated its optical performance. It gave us enough depth of focus comparable to 8% att.PSM. We are going to evaluate the possibility of full chip application in our next experiment.

For cost-effective Integrated Circuit (IC) manufacturing, it is highly desirable to use Binary-Chrome Masks (BIMs) instead of Phase Shifting Masks (PSMs). For the 70nm technology node, it is of particularly appealing if Argon Fluoride (ArF) BIMs can still be used. In this paper, we demonstrate that double dipole ArF exposure together with BIMs is capable of achieving acceptable overlapped process window for printing 70nm Critical Dimension (CD) features. The main challenge of using such a technique for IC manufacturing is how to properly decompose the original mask patterns into two separate orientation masks (vertical and horizontal). To compensate for the possible two-dimensional (2D) pattern distortion due to the strong proximity effect, a novel set of

For each generation of DRAM cell layout design to achieve ever higher device density packing, tighter pitched array cell patterns are required. Very tight-pitched patterns present a great imaging challenge for sub-100nm devices. In order to pattern the cell patterns using KrF exposure, it is necessary to make use of resolution enhancement techniques (RET) such as phase shifting mask (PSM), off-axis illumination (OAI), and optical proximity correction (OPC). At k1 approximately 0.3 imaging, we have found a combination of PSM, OAI, and OPC that allows the most robust manufacturing process. In this paper, we have applied chromeless phase lithography (CPL) with OPC on the critical DRAM cell layers, such as capacitor node and contacts. The methodology of manipulating CPL image contrast by using phase cancelling effect is proposed. The mask design flow are discussed along with the consideration of data preparation and mask manufacturing complexity for CPL. The patterning performance has been characterized by using both simulation and experimental data from printed resist wafer. Using CPL mask with optimized OAI, a 0.8 NA 248nm exposure system is well capable of printing sub-100nm DRAM cell patterns.

Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

Fostered by continued advancements in the field of optical extension technologies, optical lithography continues to extend far beyond what was thought possible only a few years ago. The application of chromeless phase lithography (CPL), or '100% transmission PSM,' has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (k1 approximately 0.2). The ability to print 70 nm lines through pitch using a 248 nm, 0.70 NA wafer scanner, QUASAR off axis illumination, and a chromeless mask (CLM) has been demonstrated. However, it was confirmed by Chen, et al., that imaging complex 2D structures with high transmission CLM reticles involves very strong optical proximity effects. The need to use high NA wafer steppers with off-axis illumination in order to apply chromeless phase lithography exacerbates these effects. This phenomenon is further magnified and the interactions become more complex as the pitch between 2D structures is decreased. The nature of the proximity effects observed with chromeless phase lithography and the means to correct for them using various optical proximity correction (OPC) methods are described and explained. Patterns representing real device- like structures are used to demonstrate that data processing algorithms are feasible which can correct for the induced proximity effects and thus make it possible to incorporate CPL technology for low-k1 production lithography.

0.7X reduction every two years, as required by Moore's Law, has increased the emphasis on low kl imaging. Low kl is a way to extend each wavelength one node (e.g., 193 nm to 65 nm, 157 to 45 nm). However, with low k 1 imaging, a significant divide opens between the desires of the chip designer and the realities of lithographic reproduction. As k 1 decreases from the safe and comfortable 0.8 value enjoyed in the 1980s, to the more stringent 0.5 adopted in production in the 90s, lithographers had to beg designers to let them do line biasing and place hammerheads at the ends of gates in order to compensate for simple proximity effects like iso-dense bias and line end shortening. Now, in the new millenium, many chip makers have to develop processes that work below 0.4 k 1 , which brings new tensions between the designer and the lithographer in the forms of design rule restrictions, 2D OPC, forbidden pitches, phase assignments, double exposure decompositions, etc. What can be done to cross this divide between chip design and lithography, as will be required to push k 1 to its limit and thus achieve the ultimate in scaling allowed by optics, is the subject of this paper.

Optical proximity effect is a well-known phenomenon in photolithography. Such an effect results from the structural interaction between the main feature and the neighboring features. Recent observations have shown that such structural interactions not only affect the critical dimension of the main feature at the image plane, but also the exposure latitude of the main feature. In this paper, it has been shown that the variation of the critical dimension as well as the exposure latitude of the main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature exposure latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features can be shown to be dependent on the pitch as well as the illumination angle. For a given illumination, the forbidden pitch lies in the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The theoretical analysis given here offers the tool to map out the forbidden pitch locations for any feature size and illumination conditions. More importantly, it provides the theoretical ground for illumination design in order to suppress the forbidden pitch phenomenon, and for scattering bar placement to achieve optimal performance as well.