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This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a $0.35~\mu \text {m}$ CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between −25 and 125 °C) and a total dose beyond 300 krad.

This paper presents an experimental set-up that combines on-chip digital techniques with off-chip Arduino-based hardware to simplify the test of widely-programmable analog-to-digital converters. The presented methodology is specially intended for analog and mixed-signal circuits which require a large number of digital signals to reconfigure their performance to different electrical specifications, environment signal conditions, battery status, etc. To this end, a serial-to-parallel register is implemented on chip in order to generate the required number of digital control signals from an input serial data provided offchip. Such serial data can be generated by using an Arduino-based hardware set-up, which can be easily programmed in MATLAB, with no additional test instruments required. As an application, the proposed method is applied to the experimental characterization of a fourth-order band-pass continuous-time ΣΔ modulator, integrated in a 65-nm CMOS technology, which can digitize signals placed at programmable carrier frequencies for software defined radio1.

This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.

This paper presents a rad-hard ASIC that implements a set of instrumentation channels that are highly configurable in terms of resolution, conversion rate, and input voltage range, providing a flexible solution for space applications requiring the digital acquisition of slow input signals with medium-to-high resolutions up to 16 bits. The differential input voltage range can be extended up to 4 V pp . The instrumentation channels combine a programmable-gain, high input impedance instrumentation amplifier and dual-slope analog-to-digital converters with radiation hardening by design (RHBD) techniques in a standard 0.35 μm CMOS technology. Experimental results demonstrate the performance of the ASIC against radiation effects up to 318 krad of TID, absence of latch-up up to at least 81.8 MeV·cm 2 /mg, SEUs LET th of 22.5 MeV·cm 2 /mg and proper operation over an extended operating temperature range.

A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 μm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach. © The Institution of Engineering and Technology 2014.

The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectronica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Tecnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35 µm CMOS technology is a first step towards the development of a mixed-signal design methodology, including an RHBD digital library suitable for use in space conditions.

Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450°C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10mm, stress gradient 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35mm, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015°/s over a bandwidth of 50 Hz.

Trabajo presentado al ECCTD celebrado en Alemania del 8 al 12 de septiembre de 2013.-- et al., Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.