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We present for the first time Si-doped HfO 2 -based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported on 1T-1R 16kbit arrays with zero bit-fail up to 105 cycles, using core logic (GO1) selector transistors. The OxRAM compatibility with GO1 transistors paves the way to arrays with minimum bitcell area of $0.066\ \mu \mathrm{m}^{2}$ at $125\mu \mathrm{A}$ programming current. We also demonstrate direct correlation between transistor compliance current variability within the 1T-1R array and the LRS distribution. This result indicates that the intrinsic LRS variability is smaller than the measured one. SPICE Monte-Carlo simulations confirm the large compliance current dispersion measured on transistors designed at minimum gate length and show path to improve even further the LRS distribution and hence the OxRAM memory window.

This work proposes a generic methodology to evaluate the feasibility of designing a MEMS resonator-based Pierce oscillator according to any given CMOS technology with the constraint of using only one single active transistor. This approach, applied to the case of a capacitive doubly-clamped beam resonator used in its in-plane fundamental vibration mode, is validated by simulations using a 0.13 μm CMOS technology.

This work is devoted to a photoreflectance (PR) study of single GaAsSb layers grown pseudomorphically on InP. Such antimonide alloys included in the base of heterojunction bipolar transistors (HBT) are expected to lead to high cut-off frequency transistors. However, many important parameters such as the nature of the InP/GaAsSb interface, the conduction band offset and the Fermi level pinning at GaAsSb surface are not well known in this system. In this study, they are determined from optical measurements performed between 8 and 300 K. Unusual evolution of the photovoltage as a function of temperature is reported in GaAsSb. Finally, a PR study of a complete HBT structure shows the potential of this technique to non-destructively characterize complex epitaxial layers, and further on to study fully processed devices under operation.

Research into strata control has been pursued at Cerchar for the last 20 years, and has led to the definition of rules for the siting of new mine workings. These rules are drawn up as a function of the ‘volume of influence’ which is exerted by existing workings. To facilitate their application by the coal producer, a computer-aided design system for steep-seam faces has been developed on a minicomputer. The main features of the interactions which occur within the volume of influence of such faces are restated and the system which has been developed for design is described, with particular emphasis on the design stages which involved graphic systems and data base management.

Les exploitations souterraines par foudroyage modifient la topographie des qu’elles atteignent des dimensions suffisantes. Les points de la surface influences par l'exploitation se deplacent horizontalement et verticalement. Les mouvements differentiels, deformations et pentes associes a ces mouvements peuvent entrainer des degâts graves aux constructions.Les exploitations partielles par longues bandes exploitees separees par de larges piliers continus permettent d'exploiter dans des conditions difficiles, sous des villes par exemple. A partir d'une etude de cas d'exploitations partielles conduite en France, au Royaume-Uni et en Australie, les auteurs proposent une methode de dimensionnement de telles exploitations. Cette methode a la particularite de tenir compte a la fois de la geometrie et de la geologie du recouvrement et du site.

The paper describes the pressiometer and its application for investigating rock deformation modulus as related to in situ elasticity, and the general condition of rocks in relation to their state of fracture in Coal Measures strata affected by mining operations.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

SYNOPSIS In Gard Colliery, the pit depth will be increased from about 100 m up to 400 m. Moreover, the geology of the coal field is very complex. Different methods for designing the pit slopes have been described. Back-analysis is the best means of characterising the mechanical behaviour of the rock mass, leading to different pairs (c m , ϕ m ). In sizing a slope higher than the analysed slope, it is necessary to choose, amongst the possible pairs (c m , ϕ m ), the one with the minimum friction angle. The obtained values are compared to laboratory results and classifications.