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Underfill process is a very important step in the flip-chip packaging because of its great impact on the reliability of electronic devices. In the control of the underfill dispensing in flip-chip packaging, an analytical model for the underfill flow behavior is required to perform the control action. Traditionally, the Washburn model is used for predicting the viscous flow behavior in the flip-chip underfill process driven by capillary forces. Unfortunately, some studies in the literature have shown that the model does not match the measured results well due to the neglect of the characteristics such as solder bump resistance and non-Newtonian behavior of underfills. Although some underfill flow models have been developed for considering these characteristics, there is no sufficient account for such a mismatch from the literature. In this article, we present an experimental investigation aimed to understand the possible causes responsible for the observed mismatch with the Washburn model. The experimental investigation confirmed that the underfill fluid used in flip-chip packaging shows a complex non-Newtonian behavior and that the Washburn model is, indeed, only applicable to the Newtonian fluid in this setting. Another contribution of the work reported in this article is the provision of measured data on a test bed which was built upon using the off-the-shelf components; as such the data can be used by other researchers to validate their theoretical findings.

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60–70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.