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Your search keyword '"Iwai, Keisuke"' showing total 99 results
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99 results on '"Iwai, Keisuke"'

1. Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU

Author

Nishikawa, Naoki, Amano, Hideharu, Iwai, Keisuke, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Yan, Zheng, editor, Molva, Refik, editor, Mazurczyk, Wojciech, editor, and Kantola, Raimo, editor

Published
2017
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2. Search Algorithm of Precise Integral Distinguisher of Byte-Based Block Cipher

Author

Kosuge, Haruhisa, Iwai, Keisuke, Tanaka, Hidema, Kurokawa, Takakazu, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Jajoda, Sushil, editor, and Mazumdar, Chandan, editor

Published
2015
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3. Information Theoretical Analysis of Side-Channel Attack

Author

Mizuno, Hiroaki, Iwai, Keisuke, Tanaka, Hidema, Kurokawa, Takakazu, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bagchi, Aditya, editor, and Ray, Indrakshi, editor

Published
2013
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4. Performance Prediction Model for Block Ciphers on GPU Architectures

Author

Nishikawa, Naoki, Iwai, Keisuke, Tanaka, Hidema, Kurokawa, Takakazu, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Lopez, Javier, editor, Huang, Xinyi, editor, and Sandhu, Ravi, editor

Published
2013
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5. Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor

Author

Nishikawa, Naoki, Iwai, Keisuke, Kurokawa, Takakazu, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Xiang, Yang, editor, Stojmenovic, Ivan, editor, Apduhan, Bernady O., editor, Wang, Guojun, editor, Nakano, Koji, editor, and Zomaya, Albert, editor

Published
2012
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18. AQSS: Accelerator of Quantization Neural Networks with Stochastic Approach

Author

Iwai Keisuke, Takakazu Kurokawa, Takeo Ueki, and Takashi Matsubara

Subjects
010302 applied physics, Artificial neural network, Computer science, business.industry, Deep learning, Quantization (signal processing), Inference, 02 engineering and technology, Logarithmic quantization, 01 natural sciences, Computer engineering, Gate array, 020204 information systems, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Artificial intelligence, Field-programmable gate array, business, Electrical efficiency
Abstract

In recent years, Deep Neural Network (DNN)s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their power consumption because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce the power consumption by replacing multipliers with shifters. However, most of them are implemented only for inference. In this paper, an Accelerator of Quantization neural networkS with Stochastic approach (AQSS) is proposed. It uses a stochastic approach for logarithmic quantization, and enables DNNs to infer or to learn using logarithmic quantization. A prototype of AQSS is implemented on a field-programmable gate array (FPGA) (Intel Arria 10 GX 1150) and synthesized with Intel Quartus Prime 17.1 Standard Edition. As a result, it is confirmed to have 1.8 times the power efficiency of GPU.

Published
2018

44. Superconducting Gap and Valence Band of Mg10Ir19B16 Studied by Laser and Synchrotron Photoemission Spectroscopy

Author

Yoshida, Rikiya, primary, Okazaki, Hiroyuki, additional, Iwai, Keisuke, additional, Noami, Kengo, additional, Muro, Takayuki, additional, Okawa, Mario, additional, Ishizaka, Kyoko, additional, Shin, Shik, additional, Li, Zheng, additional, Luo, Jianlin, additional, Zheng, Guo-qing, additional, Oguchi, Tamio, additional, Hirai, Masaaki, additional, Muraoka, Yuji, additional, and Yokoya, Takayoshi, additional

Published
2009
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48. Implementation of Symmetric Block Ciphers Using GPGPU.

Author

Nishikawa, Naoki, Iwai, Keisuke, and Kurokawa, Takakazu

Abstract

Battlefield systems have been shifting to Network-Centric Warfare since the Gulf War (1991). In such systems, computers are connected via encrypted networks, which require communications with such detailed data as video, sound, pictures, and other images in real time. However, current CPUs will be bottlenecked by encryption processing speed during heavy processing. Unfortunately, the performance increase of CPUs has been slow recently. Therefore, we have continuing in our development of a new cipher system using General Purpose computation on a Graphics Processing Unit (GPGPU). GPUs have evolved in recent years into powerful parallel computing devices, with a high cost-performance ratio. However, many factors affect GPU performance. In earlier work to gain higher AES performance using GPGPU in various ways, we obtained two technical viewpoints: (1) 16 Byte/Thread is the best granularity (2) Extended key and substitution table stored in shared memory is the best memory allocation style. This study was undertaken to test the hypothesis that these two findings are applicable to implementation of other symmetric block ciphers on two generations of GPU. In this study, we targeted five 128-bit symmetric block ciphers, AES, Camellia, CIPHERUNICORN-A, Hierocrypt-3, and SC2000, from an e-Government Recommended Ciphers List through Cryptography Research and Evaluation Committees (CRYPTREC) in Japan. We evaluated the performance of this system on each GPU using three methods: (A) throughput without data transfer, (B) throughput with data transfer and overlapping encryption processing on GPU, (C) throughput with data transfer and non-overlapping encryption processing on GPU. Results demonstrate that the throughput of implementation of SC2000 in method (A) on Tesla C2050 achieved extremely high 73.3 Gbps. Additionally, the throughput obtained using methods (B) and (C) deteriorated to 28.1 Gbps and 17.7 Gbps, respectively. Method (B) showed effective throughput with an approximately 31.1-fold higher speed compared to that obtained when using a one-core CPU. [ABSTRACT FROM AUTHOR]

Published
2012

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