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Single chip integrated power switching circuits can generate huge substrate noise, which impacts the circuit performance of noise sensitive blocks on the same chip. In this paper, the effects of several schematic and layout techniques to reduce substrate noise, including optimizing gate resistors and capacitors, merging NWELL of power devices, adding PEPI around NWELLs, using separated PADs for less noisy blocks, are validated by both simulation and silicon experiments.

This paper discusses the impact of the substrate noise generated by power switches through common substrate in bandgap voltage reference circuits, which have NPNs as main elements. It also analyzes how substrate noise affects NPN device's performance and then makes output reference voltage dc shifted in some types of bandgap circuit, which is a very fatal error in system. This analysis method of bandgap dc shift is suitable for other bandgap circuits in noisy substrate