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For the first time, chaotic signal generation with a simple and straight clamped-clamped beam resonator has been experimentally measured. The submicrometric MHz resonator and the readout circuit have been fabricated and monolithically integrated using a commercial $0.35-\mu\mathrm{m}$ CMOS technology. Extensive homoclinic chaotic motion has been obtained from the bistable cc-beam resonator and validated by means of a positive Lyapunov exponent.

We present a simple architecture for Spiking Neural Networks self-configuration. It consists in the hardware implementation of a simple Genetic Algorithm that may be used to obtain optimum network configurations. The proposed solution is applied to estimate the processing efficiency of different networks. Based on the results we develop a new performance metric to calibrate the processing capacity of SNNs.

A chaotic integrated circuit is designed and fabricated using a 0.35µm CMOS process. The circuit iterates an N-shaped transfer function using a small analog neural network. One of the advantages of the proposed circuit is its small circuit area with only 13MOS transistors. The circuit generates both an analog and a digital signal that can be used to create true random bit sequences.

We perform a comparative study of the characteristics and capabilities of a pulsed laser system that emulates single event injection available at the UIB with respect to similar pulsed laser test facilities in Europe (EADS, IMS) and the United States (JPL, NRL). A series of experimental measurements were taken on a silicon photodiode (Centronic OSD15-5T) used in a previous comparative study conducted by the mentioned centers.

A pulsed laser system has been used to induce single event upsets (SEU) in highly-scaled SRAM devices. The events are induced from the circuit topside in areas where the higher metal layers have been eliminated by design from the circuit layout. The presence of metal tracks for voltage biasing, bit-line and word-line routing, difficult carrying out measurements to obtain the minimum energy required to induce an SEU. Off-chip transient currents caused by laser pulses have been measured; data indicates that most of such current is due to photocurrents generated in the well-substrate diode.

Experimental results from a 65nm CMOS commercial technology SRAM test chip reveal a high correlation between the word-line voltage margin (WVM)-defined as the difference between the memory nominal supply voltage and the lower mean voltage applied to the word-line capable of writing a cell — and the measured circuit alpha-SER. Additional experiments show that no other memory cell robustness-related parameters (like the minimum supply voltage during hold or read) exhibit such correlation. After an initial irradiation experiment on a reduced sample circuits, the WVM technique can be used to estimate the alpha-SER levels on each particular circuit without requiring additional irradiation experiments. The technique requires a specific memory design modification that does not degrade circuit performance while circuit area increase is negligible.

This work provides practical guidelines for an efficient hardware implementation of Neural Networks. Networks are configured using a practical self-learning architecture that iterates a basic Genetic Algorithm. The learning methodology is based on the generation of random vectors that can be extracted from chaotic signals. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks.

In this work we provide design guidelines for the hardware implementation of Spiking Neural Networks. The proposed methodology is applied to temporal pattern recognition analysis. For this purpose the networks are trained using a simplified Genetic Algorithm. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks.