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The enormous availability of data on the internet and the increased computational power available in the cloud require a constant increase in the bandwidth needed to transport data across the network. In order to mitigate the cost of infrastructure, the industry has proposed standards for 56Gb/s PAM-4 interfaces that can support legacy channels in conjunction with forward error correction (FEC) techniques. The reduced signal to noise ratio (SNR) available with PAM-4 modulation vs. NRZ requires sophisticated signal processing, making DSP-based solutions very attractive in terms of performance but, so far, at the expense of extra power vs. classical analog solutions. This paper demonstrates that this trade-off can be broken and presents a compact ADC/DAC DSP-based long-reach transceiver in 7nm FinFET technology that operates seamlessly from 3.5-to60Gb/s in PAM-4 (from 1-to-30Gb/s in NRZ mode) and consumes less than 250mW at 56Gb/s. The presented IP extends the deployment of DSP-based transceivers from repeater/re-timer applications to big ASICs with a very large number of ports.

The importance and the effectiveness of any actions can be better assessed looking at the long-term results that derived from the original actions associated with it. This is what we are going to see in this paper, where we want to celebrate the research and education activity of Prof. Rinaldo Castello in the Microelectronics Lab at University of Pavia, where all of us have been students starting (in same cases) more than 25 years ago. © 2009-2012 IEEE.

This paper presents a toroidal inductor integrated in a standard 0.13 ?m CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches are followed and the results are compared; this comparison provides useful guidelines for the design of the device. A very simple ? model for low frequencies is derived from 1-port and 2-port measurements, and a good matching with general theory is observed. The coil exhibits an inductance between 0.9 nH and 1.1 nH up to 20 GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15 GHz. No self-resonance is observed within the measurement range.

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 /spl mu/W, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70/spl deg/C. Chip area (including scribe line) is 55.5 mm/sup 2/ in a 0.8 /spl mu/m N-well double-metal single-poly CMOS process with implanted capacitors.

Summary form only given. Frequency Synthesizers and clock generators are essential building blocks in almost all modern electronic systems. The Phase-locked loop (PLL) is the most suitable circuit architecture to perform the extremely diverse tasks required by the very different applications. In wireless transceivers, PLLs are used to generate high-frequency local oscillator signals with extremely low phase noise for up-conversion and down-conversion of the transmitted and received signals. For high-speed data communications very low-jitter clock signals are required. When used as clock generators for large processors, wide frequency range, fast locking time and very-low-power quiescent dissipation are absolutely mandatory. These tough specifications need to be achieved at the lowest possible power, both for the stringent requirements of portable systems, but also to reduce the issues associated with heat dissipation.

High-performance phase locked loops (PLLs) for local oscillator and clock synthesis are essential to all modern electronic communication systems. Advances in silicon technology, relentless market pressures to increase integration and reduce bill-of-material cost without sacrificing performance, and emerging market opportunities for increased functionality are continuing to fuel PLL research. The papers in this session represent a collection of innovations that address these issues.

A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mW

A complete analog front-end, with the exclusion of the frequency synthesizer, for FM broadcasting occupies 2.8 mm 2 active area in a standard 0.35 μm CMOS technology. The use of current driven passive mixer and switch capacitor polyphase filter gives +100 dBμV IIP3, 52 dB adjacent channel selectivity and +39 dB image rejection without trimming or tuning. The output noise is 390 nV//√Hz, with a conversion gain of about 39 dB. This front-end consumes only 5 mA from a 2.4 V supply © 2006 IEEE.

This paper describes a Radio Frequency (RF) front end transmitter for Wireless LAN (WLAN), designed for the most common standards, integrated in digital CMOS 0.18?m technology. It covers 802.11a/b/g specifications, concurrently working in the 2.5GHz and 5-6GHz frequency ranges. An innovative solution for the design of the LC tank allows to use a single-spiral inductor in dual resonant tank, with a strong reduction in die area. The dual band RF transmitter size is only 1mm2, the smallest ever reported in literature.

This paper presents a toroidal inductor integrated in a standard 0.13 /spl mu/m CMOS process. A very simple /spl Pi/ model for low frequencies is derived from 1-port and 2-port measurements, and a decent matching with general theory is observed. The coil exhibits an inductance of 1.1nH up to 20GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15GHz. No self-resonance is observed within the measurement range.

A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13 /spl mu/m CMOS process. The chip has an active area of 1.8mm/sup 2/ with the entire RF portion operated from 1.2V and the low frequency portion operated from 2.5V. Its key feature is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner. Measured noise figure is 3.5dB with a 1/f noise corner at 200kHz, and an IIP3 of -2dBm. The synthesizer DSB phase noise integrated over a 10MHz band is less than -36dBc. The front end reported here has one of the lowest power consumption and 1/f noise corner at 5GHz in pure CMOS ever reported so far.

This paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 /spl mu/m CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9/spl times/1.6 mm/sup 2/) 2.1 GHz /spl Sigma//spl Delta/ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth.

This paper describes a fully integrated low noise amplifier (LNA) + mixer + first filtering stage, suitable for direct conversion receivers. Its key feature is a current driven passive mixer loaded by a low impedance. Measurements performed on a 0.18 /spl mu/m CMOS prototype, confirm that this architecture, when compared to a classic one, gives a much smaller flicker noise (70 kHz 1/f corner), together with an excellent noise figure (4.4 dB integrated from 10 kHz to 1.92 MHz), while requiring only 15 mW of power. Moreover, a very good linearity is simultaneously achieved (IIP3=-1 dBm). The main limitation of the present implementation is the bandwidth of the opamp that implements the mixer load. Due to this, IIP3 degrades at higher frequencies (IIP3 about -12 dBm at 10 MHz). This is however not a fundamental limitation.

High-frequency analog filters are used in two areas. First, as preprocessing blocks in front of an A/D or as post processing blocks after a D/A. Examples are anti-alias filters for digital TVs, equalizers in digital modems and preconditioning filters in data recording channels (HDD). Second, as building blocks in the front end of a /spl Sigma//spl Delta/ converter. This paper concentrates on submicron CMOS continuous-time filters since increasing system speed requires use of the latest IC technology.

A fully-integrated PRML read/write IC with digital adaptive FIR operating up to 450 Mbit/s is presented, The chip implements an EPR4 Viterbi detector as well as a digital servo. The device is integrated in a 0.35 /spl mu/m BiCMOS technology, has a die size of 11.44 mm/sup 2/ (step and repeat) and dissipates 1.3 W (in read mode) at 450 Mbit/s.

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

A fully integrated 0.18μm CMOS ΣΔ fractional synthesizer targeting 3G wireless terminals applications is presented. This work is a practical example of a more general study on frequency fractional synthesis. A simple linear model of the system is presented and used to simulate different ΣΔ modulators topologies and to evaluate the effects of circuits non-idealities particularly on output spurious tones. Phase Frequency Detector (PFD) and Charge Pump (CP) non-linearity effects are analysed in details, the obtained results are confirmed by measurement. Solutions to overcome these limitations are given. At last, a ΣΔ quantization noise compensation technique is presented allowing to break the trade-off between Phase Locked Loop (PLL) bandwidth and high frequency noise regrowth.

A low voltage, low power CMOS single chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 AD-PCM coder/decoder, a Burst Mode Logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. It can be easily interfaced with standard microcontrollers through a parallel interface. It can operate from a 2.7 V minimum supply with operative and stand-by power consumptions of 35 mW and 25 /spl mu/W, respectively. Maximum operative supply is 5.5 V. Chip area is 55.5 mm/sup 2/ in a 0.8 /spl mu/ N-well CMOS process.

A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.

This paper presents the results of the experimental characterization of the channel thermal noise in MOSFETs belonging to a submicron gate process, with minimum gate length L=0.35 /spl mu/m. The data are compared with a noise model taking into account short-channel effects such as velocity saturation and hot carriers. The contribution of gate and substrate parasitic resistors is also evaluated and included in the model. The analysis is carried out for devices with various gate geometries, investigating the behavior of the noise-related parameters in the range of small gate-to-source overdrive voltages, which is of major concern for low-power circuits.

Data on a 7th order programmable gm-C filter in 0.35µm CMOS with 160MHz maximum pole frequency are provided. Techniques to increase the bandwidth of gm-C filters in further scaled technologies, while preserving dynamic range and accuracy, are presented. GHz passive LC filters, based on master slave tuning, are introduced.