1. A single 1.5-V digital chip for a 10 to the sixth power synapse neural network
- Author
-
Watanabe, Takao, Kimura, Katsutaka, Aoki, Masakazu, Sakata, Takeshi, and Ito, Kiyoo
- Subjects
Semiconductor chips -- Design and construction ,Neural networks -- Research ,Business ,Computers ,Electronics ,Electronics and electrical industries - Abstract
A digital-chip architecture for a 10 to the sixth power-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4 X 18.6-mm chip by using a 0.5-micrometer CMOS design rule. We fabricated a scaled-down version of the chip which has an 8-kbit DRAM cell array and confirmed its operation.
- Published
- 1993