Search

Composite materials with the composition (100-x)Cu 1.3 Mn 1.7 O 4 /xLaNi 0.6 Fe 0.4 O 3 (CMxLNF, where: x = 5, 10, 15, 20, 30, 40 and 50 wt%) were evaluated as possible coating materials for SOFC/SOEC metallic interconnects. The introduction of LaNi 0.6 Fe 0.4 O 3 into spinel matrices improved electrical conductivity compared to pure Cu 1.3 Mn 1.7 O 4. The measured Seebeck coefficient values indicate that carrier concentration increased with LaNi 0.6 Fe 0.4 O 3 content, yet the activation energy of the carriers' mobility decreased. Extensive structural and microstructural studies of selected CM/LNF systems showed that composite material components exhibited high stability in relation to one another. Additionally, LaNi 0.6 Fe 0.4 O 3 significantly improved the chemical stability of Cu 1.3 Mn 1.7 O 4 in the presence of chromia, as tested after 150 h of exposure to air at 800 °C. Finally, coatings based on selected composite powders were deposited electrophoretically on the steel and were oxidized for 1500 h in air at 750 °C, confirming that CM10LNF can be applied as effective protective-conducting coatings on low-chromium ferritic steel. • Cu 1.3 Mn 1.7 O 4 (CM) spinel / LaNi 0.6 Fe 0.4 O 3 (LNF) perovskite composites were prepared. • CM/LNF components are mutually stable after sintering. • Adding LNF to CM matrix improves electrical conductivity. • CM/LNF has better chemical stability vs chromia than reference CM. • CM10LNF coating on FSS substrate is more corrosion-resistant than CM. [ABSTRACT FROM AUTHOR]

Electromigration (EM) is a critical reliability issue in integrated circuits and is becoming increasingly significant as fabrication technology nodes continue to advance. The analysis of the hydrostatic stress, which is paramount in electromigration studies, typically involves solving complex physical equations (partial differential equations, or PDEs in this case), which is time consuming, inefficient and not practical for full-chip EM analysis. In this paper, a novel approach is proposed, conceptualizing circuit interconnect trees as a graph within a graph neural network framework. Using finite element solution software, ground truth hydrostatic stress values were obtained to construct a dataset of interconnected trees with hydrostatic stress values for each node. An improved Graph Convolutional Network (GCN) augmented with edge feature aggregation and attention mechanism was then trained employing the dataset, yielding a model capable of predicting hydrostatic stress values for nodes in an interconnect tree. The results show that our model demonstrated a 15% improvement in the Root Mean Square Error (RMSE) compared to the original GCN model and improved the solution speed greatly compared to traditional finite element software. [ABSTRACT FROM AUTHOR]

With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors. [ABSTRACT FROM AUTHOR]

In order to enhance the oxidation resistance and electrical properties of interconnects for solid oxide fuel cells (SOFCs), three Co–Ni alloy coatings with varying contents of Fe doping were prepared onto SUS 430 substrate using electroplating method and oxidized in air at 800 °C for 1000 h. The experimental results demonstrated that the alloy coating significantly enhanced both the oxidation resistance and electrical properties of the interconnect substrate. The multi-layer oxidation structure blocked Cr from diffusing outward. Notably, the (Co,Fe) 3 O 4 /(Ni,Co)O in the oxidized layer of 5% Fe doped Co–Ni coated steel completely transformed into (Fe,Co,Ni) 3 O 4 spinel layer after long term oxidation, which had the lowest activation energy and the strongest ability of restricting oxygen diffusion inward. Thus, the 5% Fe doped Co–Ni coated steel showed superior oxidation resistance (k p = 8.76 × 10−14 g2 cm−4 s−1) and excellent electrical properties (ASR = 13.19 mΩ cm2) following oxidation for 1000 h. [ABSTRACT FROM AUTHOR]

Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations. [ABSTRACT FROM AUTHOR]

This paper focuses on long‐term tests held during 1,000 h on different Membrane‐Electrode‐Interconnect Assemblies (MEIAs), consisting of an Fe‐Ni alloy interconnect and an electrochemical cell based on a Ce0.8Sm0.2O2–δ electrolyte, the double‐layer working electrode with a La2NiO4 + δ – Ce0.8Sm0.2O2–δ composite functional layer, and a LaNi0.6Fe0.4O3–δ current collector layer, and a platinum reference electrode (O2, LaNi0.6Fe0.4O3–δ|La2NiO4 + δ – Ce0.8Sm0.2O2–δ|Ce0.8Sm0.2O2–δ|Pt, O2). These tests were carried out on MEIAs with the Cr‐free 47ND alloy of the Fe–Ni system with and without surface modification at 850°C in air. The electrochemical performance of MEIAs was studied without polarization as well as under cathodic and anodic polarization with current density 0.5 A cm−2 by means of electrochemical impedance spectroscopy (EIS). The mechanism of the MEIA evolution during long‐term test is discussed. [ABSTRACT FROM AUTHOR]

Protonic ceramic electrolysis cells (PCECs) are high-temperature electrolysers (HTEs) which use ceramic electrolytes characterized by high protonic conductivity. Compared with other HTEs (e.g., solid oxide electrolysis cells, SOECs), PCEC devices work at considerably lower temperatures (i.e., 350-600 °C compared with 700-900 °C of SOEC). Nowadays, studies related to PCEC have been confined to the lab scale, with only a few attempts to scale up this technology. A single repeating unit (SRU) or a stack of large area PCEC cells is still a technological challenge and the formulation of appropriate sealants to join ceramic cells and metallic interconnects is necessary to fulfil this task. In this study, three compositions of Si-based glass-ceramic (two Na-rich and one Ba-rich) have been chemically and thermomechanically tested with materials for PCEC electrolyte (Ba(Ce,Zr) 1-y M y O 3-δ) and a ferritic stainless steel interconnect (FSS, AISI441). Afterwards, the joined sample were characterized using SEM-EDX and XRD. One of the studied compositions, a Si-based glass-ceramic containing also Na and Zr, showed promising results. The results of the microstructural analyses highlighted excellent compatibility with both the BCZY72 electrolyte and the AISI441 stainless steel after joining and ageing of 1000 h at 600 °C in static air. Moreover, this glass-ceramic system has been joined with AISI441 steel and characterized at 600 °C with the application of a voltage and different atmospheres. Good compatibility of the glass-ceramic with the AISI441 was highlighted by the microstructural characterization also in these conditions. • Glass/ceramic sealants for joining PCEC cells. • Thermochemical compatibility with SoA materials for PCEC and AISI441. • Microstructural characterization of the joined samples. • Deposition via robocasting of the sealant and characterization in static air. [ABSTRACT FROM AUTHOR]

La-doped SrTiO 3 (La x Sr 1−x TiO 3 , LST), as the promising ceramic-based interconnect material, usually needs to be sintered in reductive atmosphere at a temperature ≥ 1450 °C, such sintering condition is not friendly to cell fabrication and application. To reduce the sintering temperature of air-sintered LST, seven sintering additives, Bi 2 O 3 , Fe 2 O 3 , Li 2 O, MnO 2 , NiO, V 2 O 5 , and Co 3 O 4 , are added to the LST in this work. The results show that only Co 3 O 4 is conductive to remarkable sintering at the temperatures of 1250 °C. The relative density of LST-3%Co 3 O 4 reaches 92%, while that of the pure LST is only 48%. Moreover, the conductivity of LST-3%Co 3 O 4 achieves 8.2 S/cm at 800 °C in humidified hydrogen, which exceed 5.5 times that of the pure LST. Interestingly, LST-3%Co 3 O 4 exhibits an average TEC of 11.5 × 10−6 K−1 between 400 and 900 °C, which is very close to that of other components of SOCs. • Co 3 O 4 addition promotes the remarkable sintering of LST at a low temperature of 1250 °C. • The relative density of LST-3%Co 3 O 4 sintered at 1250 °C achieves 94.3%. • The conductivity of air-sintered LST-3%Co 3 O 4 in wet H 2 environment at 800 °C reaches 8.2 S/cm. • LST-3%Co 3 O 4 shows a matched TEC of ∼11.5 × 10−6 K−1 at 400-900 °C. [ABSTRACT FROM AUTHOR]

For Intermediate-Temperature SOFC, the lower operating temperature allows for a broader range of steel grades to be used as interconnects. This work compares the oxidation performances of six Cr 2 O 3 -forming steels and one Al 2 O 3 -forming steel, under single- and dual-atmosphere conditions. Single-atmosphere exposures in combination with Cr(VI) evaporation measurements were carried out at 600 °C. Except for AISI 430 all the Cr 2 O 3 -forming steels showed protective behaviour with similar Cr(VI) evaporation values and low area specific resistance (ASR) values. Kanthal EF101 showed the lowest level of Cr(VI) vaporisation but substantially higher ASR values. Dual-atmosphere exposures were carried out at 600 °C in Ar-5%H 2 –3%H 2 O//air-3%H 2 O. All Cr 2 O 3 -forming steels suffered various degrees of breakaway corrosion. Therefore, operation under dual-atmosphere conditions is likely the life-time-limiting failure mode. • Different grades of steels are investigated under simulated IT-SOFC conditions (single and dual-atmosphere conditions). • Similar Cr(VI) evaporation levels for all Cr 2 O 3 -forming steel and very low levels for the Al 2 O 3 -forming alloy are observed. • Low ASR values for most Cr 2 O 3 -forming steels and higher ASR values for Al 2 O 3 -forming alloy are observed. • Under dual-atmosphere all Cr 2 O 3 -forming steels exhibit breakaway corrosion while the Al 2 O 3 -forming alloy stays protective. • Laves phase precipitates may increase the corrosion of FeCr alloys under dual-atmosphere conditions. [ABSTRACT FROM AUTHOR]

The effects of doping transition metal and rare-earth elements on the Mn 1.5 Co 1.5 O 4 coating were investigated to improve the oxidation resistance and electrical conductivity of coating/steel. The results show that transition metal improves the coating densification, and rare-earth element inhibits the formation of highly resistive Cr 2 O 3 layers. The modified coating increases the octahedral sites of variable valence ion concentration. The area-specific resistance (ASR) of the modified coating is reduced by 2–3 times compared with that of the conventional MnCo coating. The enhanced antioxidant properties of Cu-modified coatings during short-term oxidation processes. • Transition metal and rare earth modified MnCo coatings was proposed for interconnect. • Investigated the effect of doping content on coating properties. • The MnCoCu0.3–0.5 coating obtained great oxidation resistance. • Revealed the electrical conductivity mechanism of the coating. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-broadband, low-loss, flexible liquid crystal polymer substrate-to-substrate interconnect with a bandwidth of more than 130 GHz. The transition discontinuity was minimized by maintaining both the reference impedance and the electromagnetic field conformity across the transition from alumina substrate to flip-chip foil. Therefore, more than 600 $\mu$m long flexible flip-chip interconnects can be realized for bridging millimeter-wave sub-modules and enabling ultra-broadband heterogeneous system design with a measured return loss of above 20 dB. Furthermore, the interconnect can realize ramp interconnections between monolithic microwave integrated circuits or substrates with different substrate heights due to the flexible foil substrate. Minimum parasitic radiation at the transition is realized through a closely spaced signal-to-ground connection. Furthermore, the robustness of the proposed interconnect against lateral misalignment in the assembly is presented through simulation and measurement. An outstanding insertion loss of less than 0.3 dB per transition over a bandwidth of more than 130 GHz is shown.

Achieving historically anticipated improvement in the performance of integrated circuits is challenging, due to the increasing cost and complexity of the required technologies with each new generation. To overcome this limitation, the exploration and development of novel interconnect materials and processes are highly desirable in the microelectronics field. Molybdenum (Mo) is attracting attention as an advanced interconnect material due to its small resistivity size effect and high cohesive energy; however, effective processing methods for such materials have not been widely investigated. Here, we investigate the electrochemical behavior of ions in the confined nanopores that affect the electrical properties and microstructures of nanoscale Mo and Mo–Co alloys prepared via template-assisted electrodeposition. Additives in an electrolyte allow the deposition of extremely pure metal materials, due to their interaction with metal ions and nanopores. In this study, boric acid and tetrabutylammonium bisulfate (TBA) were added to an acetate bath to inhibit the hydrogen evolution reaction. TBA accelerated the reduction of Mo at the surface by inducing surface conduction on the nanopores. Metallic Mo nanowires with a 130 nm diameter synthesized through high-aspect-ratio nanopore engineering exhibited a resistivity of (63.0 ± 17.9) μΩ·cm. We also evaluated the resistivities of Mo–Co alloy nanowires at various compositions toward replacing irreducible conventional barrier/liner layers. An intermetallic compound formed at a Mo composition of 28.6 at%, the resistivity of the Mo–Co nanowire was (58.0 ± 10.6) μΩ·cm, indicating its superior electrical and adhesive properties in comparison with those of conventional barriers such as TaN and TiN. Furthermore, density functional theory and non-equilibrium Green’s function calculations confirmed that the vertical resistance of the via structure constructed from Mo-based materials was 21% lower than that of a conventional Cu/Ta/TaN structure.

While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7 nm node. Based on interconnect resistance values from technology computer-aided design (TCAD) simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin–orbit torque (SOT) MRAM and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays.

Metallic interconnect coatings, consisting of MnCo 2 O 4 spinel, were effectively applied to Crofer 22 APU using the electrophoretic deposition (EPD) method in both H 2 O: ethanol and pure ethanol solvents. The primary goal of this method was to prevent chromium migration, minimize evaporation, and control the oxidation rate. The study aimed to assess the quality, adhesion, and thickness of the Mn–Co coating, with the objective of achieving a consistent and uniform layer. The results indicated a preference for pure ethanol solvent over H 2 O: ethanol (40:60 %Vol) for Mn–Co particles. Furthermore, the agglomeration of Mn–Co particles was notably lower (approximately 7 times) in ethanol compared to H 2 O: ethanol. The morphology and surface roughness of the sintered Mn–Co coating on the alloy were examined using scanning electron microscopy (SEM) and confocal laser scanning microscopy (CLSM). A uniform and dense coating was successfully attained using pure ethanol solvent at a solid concentration of 10 g/L, with 0.5 g/L of iodine serving as a disperser. The deposition process, carried out at a voltage of 30V for 20 s, resulted in a coating with a thickness of 7.4 ± 0.3 μm and a surface roughness of 0.75 ± 0.5 μm. [Display omitted] • Dispersed Mn–Co particles in ethanol were more appropriate for EPD process. •A uniform and crack-free coating applied onto Crofer 22 APU using the EPD method. •The optimal voltage and deposition time for EPD method were 30 V and 20 s. •The optimal coating thickness and surface roughness were 7.4 ± 0.3 and 0.75 ± 0.5 μm. [ABSTRACT FROM AUTHOR]

A key component of a Solid Oxide Fuel Cell (SOFC) is the interconnect, which connects individual fuel cells in series to form a fuel cell stack. The interconnect is exposed to air and fuel in parallel; these so-called dual-atmosphere conditions cause severe corrosion on the air-side. This work investigates interconnect coatings that can mitigate this effect. Physical Vapour Deposition (PVD) coatings of Cr 2 O 3 , CeO 2 , YSZ, and Al 2 O 3 on ferritic stainless steel (AISI 441) were exposed under dual-atmosphere conditions for up to 3000 h. The evolution of the corrosion products was evaluated using optical microscopy and Scanning Electron Microscopy (SEM) in combination with Energy-dispersive x-ray Spectroscopy (EDS). The SEM analysis showed that a chromia coating was not sufficient to reduce the dual-atmosphere effect, while other coatings on the fuel-side suppressed the dual-atmosphere effect by forming a barrier to hydrogen permeation. The best outcomes were observed with Al 2 O 3 coatings on the fuel-side, which drastically reduced the dual-atmosphere effect. A 30 nm Al 2 O 3 coating displayed acceptable Area-Specific Resistance (ASR). • Fuel side PVD coatings as barriers against hydrogen ingress are investigated. • Coatings can significantly improve the corrosion resistance on the air side. • A CeO 2 coating has good conductivity and provides acceptable corrosion protection. • A 30 nm Al 2 O 3 layer provides good barrier properties and acceptable ASR. [ABSTRACT FROM AUTHOR]

Stacking of solid oxide cells (SOC) requires that a robust and durable electrical contact is established between the cell and the interconnect. In this work, we present a contact layer solution for the SOC air side based on the concept of reactive oxidative bonding in which metallic Mn-Co and Mn-Cu particles are oxidized in-situ during stack initiation or operation to form robust well-conductive spinel oxides. The long-term (3000 h) stability of the new contact layers is evaluated by measuring the area specific resistance (ASR) during aging in air at 750 °C and 850 °C, and during thermal cycling. Both Mn-Co and Mn-Cu layers are found to be well compatible with a CeCo coated 441 steel interconnect material, and do not significantly contribute to the resistance across the stack element. The resistance is dominated by the coated steel. [ABSTRACT FROM AUTHOR]

The Fe/Mn-modified Mn–Co spinel oxides (MCO) are coated on SUS430 interconnect to protect against oxidation and chromium diffusion by wet spray followed by nitrate solution impregnation for intermediate-temperature solid oxide fuel cell (IT-SOFC) application. 1000 h oxidation tests at 800 °C show that the FeMCO-coated sample have the minimum parabolic rate constant (9.02 × 10−7 mg2cm−4s−1), which is lower than half of the uncoated sample. The area-specific resistance (ASR) of the FeMCO-coated sample is 6.41 mΩcm2 at 800 °C after 1000 h oxidation, which is much lower than the MCO sample (19.38 mΩ cm2) and the uncoated sample (186.84 mΩ cm2). The samples microstructures are examined by scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS). Based on a novel approach, the dimensionless fluid numbers are related to the high-temperature conductivity of coated interconnects, and the inward diffusion of oxygen is introduced as the limiting factor for oxide-scale growth of coated interconnects. • Fe/Mn-modified Mn–Co-spinel coatings are formed via spraying and impregnation. • Coated samples are oxidized for 1000 h at 800 °C in air. • Fe-modified Mn–Co coating shows the lowest oxidation rate and ASR. • A fluid-flow based model is proposed to predict ASR with scale growth. [ABSTRACT FROM AUTHOR]

The spinel-based coatings have been applied to limit interconnect degradation issues for the metallic interconnects in solid oxide fuel cells. This work provides the recent advances in spinel-based protective coatings produced by viable and effective electrochemical methods on metallic interconnects. Two-step calcination appears to be the usual way to densify spinel by electrophoretic deposition. The electroplating employs a simple approach to depositing dense alloy coatings by co-deposition of metals with similar potential. The electrophoretic deposition/electroplating method is expected to prepare more particle contents than composite electrodeposition. The polymetallic spinel is further designed to improve the high temperature oxidation performance as the prospective coating by EPD or electroplating method. • This study describes and compares 4 electrochemical methods from recent advances. • Electrochemical methods are effective for preparation of spinel protective coating. • EPD provides the best performance for the bimetallic spinel. • Polymetallic spinel shows the superior overall performance. [ABSTRACT FROM AUTHOR]

Scattering source‐based mean free path (MFP) and circuit modeling are proposed for three different configurations of undoped multilayer graphene nanoribbon (U‐MLGNR) (viz. horizontal top‐contact (HTC), horizontal side‐contact (HSC), and vertical top‐contact (VTC)). A similar analysis is carried out for doped HTC‐MLGNR (D‐HTC‐MLGNR) considering dopants viz. Li, FeCl3, and AsF5, for a temperature range of 300–500 K. The optimistic intrinsic‐phonon limited (Λeff,1(T)) and realistic scattering limited (Λeff,2(T)) effective MFP models are considered to derive the equivalent resistance of MLGNR. The performance of MLGNR variants, considering Λeff,1(T) and Λeff,2(T), is compared to copper (Cu) (with smooth and rough surface) in terms of coupled line crosstalk‐induced delay (XT‐D). The results show that the MLGNR variants outperform Cu interconnects in terms of XT‐D, for Λeff,1(T). However, structural edge roughness being the dominant scattering source in Λeff,2(T), severely degrades the performance of MLGNR variants in comparison to Cu counterparts. Moreover, for Λeff,1(T) and Λeff,2(T), Li‐D HTC‐MLGNR outperforms other MLGNR variants. Also, among the MLGNR variants, U‐VTC‐MLGNR exhibits a minimum average relative penalty of 21.58 × 102% in terms of XT‐D, when Λeff,2(T) is considered as against Λeff,1(T). Li‐D HTC‐MLGNR with optimized width exhibits 10.59× lower XT‐D and 8.85× higher XT‐D for Λeff,1(T) and Λeff,2(T), respectively, compared to smooth Cu. The optimized Li‐D HTC‐MLGNR demonstrates a reduction of 85.48% and 74.67% in XT‐D values for Λeff,1 (T) and Λeff,2 (T), respectively, when compared to mixed carbon nanotube (MCNT) bundle interconnects. [ABSTRACT FROM AUTHOR]

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 um to 100 um), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

Electromigration (EM) is a critical reliability issue in integrated circuits and is becoming increasingly significant as fabrication technology nodes continue to advance. The analysis of the hydrostatic stress, which is paramount in electromigration studies, typically involves solving complex physical equations (partial differential equations, or PDEs in this case), which is time consuming, inefficient and not practical for full-chip EM analysis. In this paper, a novel approach is proposed, conceptualizing circuit interconnect trees as a graph within a graph neural network framework. Using finite element solution software, ground truth hydrostatic stress values were obtained to construct a dataset of interconnected trees with hydrostatic stress values for each node. An improved Graph Convolutional Network (GCN) augmented with edge feature aggregation and attention mechanism was then trained employing the dataset, yielding a model capable of predicting hydrostatic stress values for nodes in an interconnect tree. The results show that our model demonstrated a 15% improvement in the Root Mean Square Error (RMSE) compared to the original GCN model and improved the solution speed greatly compared to traditional finite element software.

With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors.

The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the importance of protecting on-chip bus interconnects and reviews existing protection approaches used in processors for mission and safety-critical processors. The protection approaches are sorted into three groups: information, temporal, and spatial redundancy. Because the final selection of the protection approach depends on the use case and performance, power, and area demands, the three groups are compared according to their fundamental properties. For better context, the review also contains information about existing solutions for protecting the internal logic of the cores and external memories. This review should serve as an entry point to the domain of protecting the on-chip bus interconnect and interface of the core. [ABSTRACT FROM AUTHOR]

This research was conducted in the context of the semiconductor market, with a demand for high-performance and highly integrated semiconductor systems that simultaneously enhance performance and reduce chip size. Scaling down the metal line and via in back-end-of-line (BEOL) structures is essential to efficiently deliver power to scaling down devices. This study utilized the finite element method (FEM) simulation technique to model the heat and current distribution for enhancing the efficiency of scaled-down structures. Due to current flow bottlenecks, an increase in the area ratio of the via to metal line (as the via becomes relatively smaller) leads to a temperature rise due to Joule heating. This trend follows a second-degree polynomial form, and the point where the temperature doubles compared to when the area ratio is one is situated at an area ratio of three. The temperature increase caused by Joule heating ultimately leads to destruction of the via, which directly affects the reliability of the BEOL structure. These experimental results can provide guidelines for designing with reliability considerations in mind, particularly in today's semiconductor systems where significant scaling down is required in interconnect structures. They can also be widely applied to research aimed at developing interconnect structures that enhance reliability. [ABSTRACT FROM AUTHOR]

Solid oxide electrolysis cell stacks are expected to experience dynamic conditions when using renewable electricity derived from wind or solar power. To address this scenario, (Mn,Co) 3 O 4 (MCO)-coated Crofer 22 APU interconnect coupons are subjected to thermal cycling, and intermittent current density, with gas compositions relevant to high-temperature electrolysis (elevated steam:hydrogen ratio and oxygen content). Defects are also intentionally introduced in the MCO coating, to assess whether the difference in oxidation properties of the adjacent coated and uncoated (defective) surfaces causes sufficient stress to damage the protective oxide scale. Specimens with defects are subjected to oxidation for 1000 h at 800 °C, or thermal cycling. Before thermal cycling, some specimens are pre-oxidized to create a thick oxide scale to mimic the scale thickness expected after ∼30 kh operation. In all cases, the coating and oxide scale remain well adhered with no cracking observed. Area-specific resistance (ASR) is monitored in both single-atmosphere and dual-atmosphere conditions, and the ASR is stable and is not impacted by dynamic cycling of the current density. This work provides confidence that the MCO coated interconnect will function as needed in dynamic operation conditions, even with coating defects. • Oxidation of coated interconnects is studied in SOEC environments. • Coating defects are intentionally added, and the scale remains protective. • Thick scale is generated before thermal cycling, and the scale does not crack. • The ASR is stable in dual and single atmospheres, with intermittent current. [ABSTRACT FROM AUTHOR]

In this study, we designed a 6T‐SRAM cell using 16‐nm CMOS process and analyzed the performance in terms of read‐speed latency. The temperature‐dependent Cu and multilayered graphene nanoribbon (MLGNR)‐based nano‐interconnect materials is used throughout the circuit (primarily bit/bit‐bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano‐interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading‐0 and reading‐1 operations. To execute the reading operation, the CMOS technology, that is, the16‐nm PTM‐HPC model, and the16‐nm interconnect technology, that is, ITRS‐13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high‐speed memories using different nano‐interconnect materials. [ABSTRACT FROM AUTHOR]

In this paper the DSM (Deep sub micron) and lower node technologies device dimensions are reduced. Compared to logic functional blocks interconnects dynamic power consumption plays most precarious factor. The most effective way to save the dynamic power in wires is to reduce the number of transitions by using the data encoder. In this paper we proposed a inverse based algorithm with mathematical proof and simple architecture. it is having the different options lower bit inversion, upper bit inversion, all bit inversions and no bit inversion, the data selection based on the which option saves the more power. It is having the simple and compact architecture and it offers less delay compared to related methods.

Commercial La0.6Sr0.4Co0.2Fe0.8O3-δ powder was used for preparation of corresponding perovskite films on commercial Crofer 22 APU high chromium steel by pulsed laser deposition. The obtained films PLD1 and PLD2 with a thickness of 1.1 and 0.35 μm, respectively, were dense and homogeneous, with good adhesion to the polished surface. Oxidation studies of the samples were carried out in air at 800°C for 200h. The calculated parabolic rate constant kp after isothermal oxidation for the PLD1 sample was 4.10 × 10−14 g2cm−4s−1 and was approximately four times lower than the oxidation rate determined for the PLD2 sample. As a result of the oxidation process, in both cases, a thin oxide layer of chromia and Mn1.5Cr1.5O4 spinel was formed on the steel/film interface. In addition, small amounts of manganese-chromium spinel crystals were observed on the films’ surfaces. Values of the specific electrical resistance at 800 °C after 100 h of the experiment were 0.06 and 0.038W•cm2 for PLD1 and PLD2, respectively. The results indicate that the applied coatings meet the criteria set upon protective-conductive layers for interconnect materials, for the IT-SOFCs (intermediate-temperature solid oxide fuel cells) applications.

In order to investigate the performance of Cu–Mn spinel coatings used for solid oxide fuel cell interconnect, a series of Cu x Mn 3-x O 4 (x = 0.6, 0.8, 1.0, 1.1, 1.2, and 1.3) coatings are prepared using supersonic spraying via subsequent sintering. The chemical composition and distribution, lattice structures, morphology, and electrical properties are characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS), and area-specific resistance (ASR) measurements. The experimental results show that with the increase of Cu concentration in the coatings, the crystalline structure gradually changes from inverse spinel into normal spinel, especially when 0.6 ≤ x ≤ 1.0. An improvement in electrical conductivity accompanies the crystalline structural transformation. The coatings show high electrical conductivity when 1.0 ≤ x ≤ 1.3, especially from 600 to 800 °C. However, the scale (mainly Cr 2 O 3) is reactive to the Cu x Mn 3-x O 4 coatings (especially when 1.1 ≤ x ≤ 1.3) at elevated temperatures. During the long-term experiment, the reaction corrodes the coatings, consumes the materials in coatings and scale, and forms new phases (mainly (Cu,Mn,Cr) 3 O 4 and (Cr,Mn) 3 O 4). This phenomenon (Cr-corrosion) aggravates the Cr diffusion, causes a quick increase of ASR, and weakens the oxidation resistance. The adverse effects of Cr-corrosion can be alleviated by appropriately lowering the operating temperature. Among the coatings, Cu 1.0 Mn 2.0 O 4 exhibited good electrical conductivity and soundness against the Cr-corrosion and can be considered a competitive candidate for SOFC applications. [ABSTRACT FROM AUTHOR]

Interconnects have become a major obstacle in chip scaling. Spoof surface plasmon polariton (SSPP) modes have gained attention for their ability to manipulate light beyond diffraction limits at a given frequency, leading to SSPP interconnects. This article investigates the transmission characteristics of SSPP interconnect pairs placed side by side in the terahertz frequency range with comprehensive performance analysis. The proposed SSPP waveguide pair exhibits a maximum transmission coefficient of around −0.05 dB in the −3 dB band in the terahertz frequency range. Due to field confinement near the metal–dielectric interface, energy remains confined for the designed SSPP interconnect pair system. The proposed SSPP structure shows several bands in the terahertz frequency range, whereas conventional interconnects shows almost zero transmission at such frequencies. Additionally, the effect of geometric parameters on transmission coefficients (S 21 ) and coupling coefficients (S 41 ) has been investigated. Moreover, it has been shown that the bandwidth, as well as the upper cutoff frequency, can be tuned by varying the geometric parameters such as groove height, groove width and groove density. Since global interconnects undergo bending in actual circuits during distant data transmission on chips, geometric mismatches may occur between adjacent pairs of SSPP interconnects. Hence, it has also been examined how bending and mismatches affect transmission and coupling coefficients. Several SSPP schemes have been simulated, among which the best performance is obtained with 2 μ m mismatch in groove height. For this optimized design, two corrugated metal interconnects are considered with groove heights of 20 μ m and 22 μ m, respectively, a groove width of 3 μ m, a period of 20 μ m, and the number of grooves at 50. For this particular configuration, an ultra-wide passband is found having a bandwidth of almost 400 GHz, with a signal reflection of below −12 dB and little insertion loss of ∼−1.43 dB. [ABSTRACT FROM AUTHOR]

Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front‐end‐of‐line (FEOL) processes have provided various solutions to this predicament, whereas the back‐end‐of‐line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem‐solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self‐assembled molecular layers, high‐entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state‐of‐the‐art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials‐based implementation strategy to bridge the gap between academia and industry. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an efficient optimization strategy based on the Stoyan and Yaskov algorithm to maximize the tube density of randomly distributed mixed carbon nanotube bundles (RMCBs) for configuring optimum performance of on‐chip interconnects. Optimizing tube density has proposed eight different RMCB (RMCB1–RMCB8) structures of a varying number of carbon nanotubes (CNTs), where RMCB1 has the maximum CNTs. Moreover, the ABCD technique adequately analyzes the temperature‐dependent frequency and stability characteristics of a three‐line RMCB interconnect placed on smooth and rough substrates (SiC, BN, and SiO2). The smooth substrate material has the best 3‐dB bandwidth compared with rough SiC substrate, followed by BN and SiO2 for all RMCB structures, and among all structures, the RMCB8 has the best 3‐dB bandwidth. The relative stability of RMCB1 is improved by 134.2% and 22.7% w.r.t. RMCB8 placed on a smooth and rough SiC substrate, respectively. Whereas bandwidth of the RMCB1 is reduced by 26% and 88.5% w.r.t. RMCB8 placed on a smooth and rough substrate, respectively. Hence, there is a tradeoff between the bandwidth and the relative stability as the number of CNT increases. Therefore, RMCB3 placed on a smooth substrate and RMCB4 placed on a rough SiC substrate are considered the best‐optimized RMCB interconnects to maintain a balance between the two. [ABSTRACT FROM AUTHOR]

An ultra-wideband (UWB) interconnect technology using indium phosphide (InP)-based transitions for coupling the output signals from terahertz (THz) photodiodes featuring coplanar waveguide (CPW) outputs to low-loss dielectric rod waveguides (DRWs) is presented. The motivation is to exploit the full bandwidth offered by THz photodiodes without limitations due to standard rectangular waveguide interfaces, e.g., for future high data rate THz communications. Full electromagnetic wave simulations are carried out to optimize the electrical performance of the proposed InP transitions in terms of operational bandwidth and coupling efficiency. The transitions are fabricated on 100-µm-thin InP and integrated with silicon (Si) DRWs. Experimental frequency domain characterizations demonstrate efficient THz signal coupling with a maximum coupling efficiency better than − 2 dB. The measured 3-dB and 6-dB operational bandwidths of 185 GHz and 280 GHz, respectively, prove the multi-octave ultra-wideband features of the developed interconnect technology. The 6-dB operational bandwidth covers all waveguide bands between WR-12 to WR-3, i.e., a frequency range between 60 and 340 GHz. In addition, the multi-octave performances of the fabricated interconnects were successfully exploited in proof-of-concept THz communication experiments. Using intermediate frequency orthogonal frequency division multiplexing (OFDM), THz communications are demonstrated for several frequency bands using the same interconnect. Considering soft-decision forward error correction, error-free transmission with data rates of 24 Gbps at 80 GHz and 8 Gbps at 310 GHz is achieved. [ABSTRACT FROM AUTHOR]

The evolution of Co coating in solid oxide fuel cells (SOFCs) under low and medium temperatures (<700 °C) is different from that under high temperatures. In this context, the oxidation corrosion of 441 ferritic stainless steel (FSS) with a Co coating in air under 650 °C was investigated. The results indicated that the Co coating was oxidized rapidly and a Co3O4 spinel layer formed in the initial exposure of 5 min, which improved the oxidation resistance of 441 steel. After oxidation at 650 °C for 120 h, a Cr2O3 layer with a thickness of 0.2–0.4 μm was observed on the surface of bare 441 steel, while the surface oxide scale of Co-coated 441 steel samples was composed of an inner Cr2O3 and Fe2O3 solid solution (0.1–0.3 μm thick), an intermediate (Fe, Co)3O4 layer and an outer Co3O4 spinel layer, respectively. The Co-coated 441 steel sample exhibited better electrical properties. After oxidation at 650 °C for 120 h, the area-specific resistance (ASR) of the Co-coated steel was 3.73 mΩ·cm2, which was 25.4% lower than that of bare 441 steel as 5 mΩ·cm2. Furthermore, the thermal growth process and protection mechanism of Co coating at 650 °C were discussed. [ABSTRACT FROM AUTHOR]

The downscaling of metal lines in CMOS devices to subnanometer sizes leads to an increase in their resistivity. Thus, the lower electron mean free paths of Ru, Rh, and Ir make them promising materials to replace Cu in conventional interconnected structures with sub-ten-nanometer dimensions. In this study, we investigate their scaling effects on the resistivities of metal lines with thicknesses of 4–32 nm. The resistivities of Ru, Rh, and Ir as-deposited films prepared via sputtering are lower than that of a Cu film with a sub-ten-nanometer thickness. Despite their similar electron mean free paths, the difference in their bulk resistivities lead to Ir and Rh having lower resistivities than Ru, even after annealing at 400 °C. Their resistivities before and after annealing were fitted with equations based on the Fuch–Sondheimer and Mayadas–Shatzkes models, which assess the contributions of surface and grain boundary scatterings, respectively. We determined that grain boundary scatterings have a significant effect on the resistivities of Ru, Ir, and Rh, whereas surface scatterings have a minimal effect. In addition, in the case of Ru, the effect of the surface roughness on the resistivity was also investigated by measuring the resistivity of Ru films deposited by atomic layer deposition. A high surface RMS roughness of 1–2 nm causes a significant increase in the resistivity at thicknesses below 10 nm that cannot be explained by the aforementioned models. These results present multiple points for consideration when applying short mean free path metals to finite size interconnects.