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A comprehensive overview of PowderMEMS—a novel back-end-of-line-compatible microfabrication technology—is presented in this paper. The PowderMEMS process solidifies micron-sized particles via atomic layer deposition (ALD) to create three-dimensional microstructures on planar substrates from a wide variety of materials. The process offers numerous degrees of freedom for the design of functional MEMSs, such as a wide choice of different material properties and the precise definition of 3D volumes at the substrate level, with a defined degree of porosity. This work details the characteristics of PowderMEMS materials as well as the maturity of the fabrication technology, while highlighting prospects for future microdevices. Applications of PowderMEMS in the fields of magnetic, thermal, optical, fluidic, and electrochemical MEMSs are described, and future developments and challenges of the technology are discussed. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. [ABSTRACT FROM AUTHOR]

This article investigates the gallium nitride based bridgeless dual single-ended primary inductor converter (SEPIC) power factor correction (PFC) with full input voltage range zero-voltage-switching (ZVS) turn-on for the application of step down ac–dc converter. The operation principle for the bridgeless Dual-SEPIC PFC and the theoretical analysis for the ZVS operation has been investigated. Furthermore, a new magnetic integration has been proposed to assemble all three inductors, including one input inductor and two output side inductors into one E-I-E core. The integrated inductor reduces the total ferrite volume and makes the converter more compact. The inductance design for ZVS SEPIC PFC and the magnetic reluctance modeling for the E-I-E core with the coupled inductor has been analyzed. The effective equivalent inductance of the input inductor can be implemented with a much less number of turns by a carefully designed coupling coefficient. Finally, a 300 W GaN-based MHz bridgeless dual-SEPIC PFC with the integrated inductors is developed and tested with full–range ZVS, 97% peak efficiency based on the ZVS extension strategy. [ABSTRACT FROM AUTHOR]

This paper presents a measurement and simulation studies on the near magnetic field radiated by an integrated inductor with magnetic material. It presents the probe influence on the measured magnetic field and the importance of the probe position. These studies are performed in simulation using HFSS software and in measurement using scan near field bench. A very good agreement between measurement and simulation is shown. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.

In this article, the simulation results, the technological steps of manufacturing, and the characterization results at low and medium frequencies (20 MHz to a few hundred MHz) of integrated inductors with two magnetic layers are presented. Simulation realized with the high-frequency structure simulator (HFSS) software allows the impact of the vertical and horizontal air gaps on the inductance value for inductors with two magnetic layers to be determined. Inductors with two magnetic layers are manufactured with magnetic thicknesses varying from 100 to $500~\mu \text{m}$. The interest of this new manufacturing process is compatible with most ferrite. The measurement results show good agreement with the simulation results. By minimizing the vertical air gap, the inductance value increases with a ratio equal to the relative permeability of the magnetic material when field lines are totally canalized into the magnetic layers. The extracted resistance evolution of the inductor on the frequency is explained by taking into account the skin and proximity effects for the conductor losses and the iron losses for the magnetic material. [ABSTRACT FROM AUTHOR]

High-performance and small-size on-chip inductors play a critical role in contemporary radio-frequency integrated circuits. This work presents a reliable surrogate modeling technique combining low-fidelity EM simulation models, response surface approximations based on kriging interpolation, and space mapping technology. The reported method is useful for the development of broadband and highly accurate data-driven models of integrated inductors within a practical timeframe, especially in terms of the computational expense of training data acquisition. Application of the constructed surrogate model for rapid design optimization of a compact on-chip inductor is demonstrated. The optimized EM-validated design solution can be reached at a low computational cost, which is a considerable improvement over existing approaches. In addition, this work provides a description and illustrates the usefulness of a multi-fidelity design optimization method incorporating EM computational models of graduated complexity and local polynomial approximations managed by an output space mapping optimization framework. As shown by the application example, the final design solution is obtained at the cost of a few high-fidelity EM simulations of a small-size integrated coil. A supplementary description of variable-fidelity EM computational models and a trade-off between model accuracy and its processing time complements the work.

Identification of the best trade-offs between conflicting design objectives allows for making educated design decisions as well as assessing suitability of a given component or circuit for a specific application. In case of inductors, the typical objectives include maximization of the quality factor and minimization of the layout area, as well as maintaining a required inductance at a given operating frequency. This work demonstrates low-cost multi-objective design optimization of integrated inductors. The primary technique utilized here is a point-by-point Pareto front exploration where subsequent Pareto-optimal designs are obtained by moving along the front using local search methods. Considerable reduction of the design cost is achieved by extrapolating inductor dimensions at the subsequent optimal point, based on already available data as well as size constraints. The proposed methodology is verified using two examples of spiral inductors implemented in 65-nm CMOS technology. Comparisons with point-by-point optimization without extrapolation are also provided. [ABSTRACT FROM AUTHOR]

Ultra-low profile integrated magnetic solenoid inductors and transformers were fabricated on 200 mm wafers with back end of line (BEOL) techniques. The process uses thick copper metallization, polymer coating, and laminated amorphous Co–Zr–Ta magnetic material. The substrate was thinned to obtain an inductor thickness of $150~\mu \text{m}$. By varying the core size and winding pitch, a large set of inductance values was obtained, from 20 to 500 nH in the 1 MHz to 3 GHz frequency range. We report a record inductance surface density of $3500\,\,\text {nH}\cdot \text {mm}^{\mathrm {-2}}$ and quality factors up to 23, and transformers with high coupling factors (>0.95). [ABSTRACT FROM AUTHOR]

The knowledge-intensive radiofrequency circuit design and the scarce design automation support play against the increasingly stringent time-to-market demands. Optimization algorithms are starting to play a crucial role; however, their effectiveness is dramatically limited by the accuracy of the evaluation functions of objectives and constraints. Accurate performance evaluation of radiofrequency passive elements, e.g., inductors, is provided by electromagnetic simulators, but their computational cost makes their use within iterative optimization loops unaffordable. Surrogate modeling strategies, e.g., Kriging, support vector machines, artificial neural networks, etc., arise as a promising modeling alternative. However, their limited accuracy in this kind of applications has prevented a widespread use. In this paper, inductor performance properties are exploited to develop a two-step surrogate modeling strategy in order to evaluate the behavior of inductors with high efficiency and accuracy. An automated design flow for radiofrequency circuits using this surrogate modeling of passive components is presented. The methodology couples a circuit simulator with evolutionary computation algorithms such as particle swarm optimization, genetic algorithm or non-dominated sorting genetic algorithm (NSGA-II). This methodology ensures optimal performances within short computation times by avoiding electromagnetic simulations of inductors during the entire optimization process and using a surrogate model that has less than 1% error in inductance and quality factor when compared against electromagnetic simulations. Numerous real-life experiments of single-objective and multi-objective low-noise amplifier design demonstrate the accuracy and efficiency of the proposed strategies. [ABSTRACT FROM AUTHOR]

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process. [ABSTRACT FROM AUTHOR]

This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure which aims to obtain adjustment factors associated to main physical inductor characteristics, allowing to estimate more accurate series inductance values that can be used in design stage. Experimental measurements of diverse square inductor geometries are shown and compared with previous approaches in order to demonstrate and validate presented approach. [ABSTRACT FROM AUTHOR]

This paper presents integrated inductors with Co-Zr-Ta-B (CZTB) thin films on flexible organic substrates for MHz–GHz applications. This paper demonstrated the fabrication and characterization of magnetic thin-film inductors on flexible organic substrates, such as polyimide and Ajinomoto build-up film thin films. These films have thicknesses of only tens of micrometer and thus are very flexible compared to the same inductor structures fabricated on rigid substrates, such as quartz. The magnetic films on flexible substrates were observed to maintain similar magnetic properties compared with those on Si substrate, but with greater coercivity likely due to the increased roughness of the substrate surface. The fabricated thin-film inductors on organic substrates with inductance $L$ , measured by RF characteristics, have shown significantly increased inductance compared to air-core inductors (without magnetic core materials). This paper also demonstrated a high frequency response, clearly over GHz, consistent with the CZTB type of materials. The frequency response, as well as inductance and Q values, remains similar even after many iterations of bending to a large degree, indicating the robustness of the inductor on flexible organic substrates, as well as that of the magnetic thin films. [ABSTRACT FROM AUTHOR]

In recent years, the application of evolutionary computation techniques to electronic circuit design problems, ranging from digital to analog and radiofrequency circuits, has received increasing attention. The level of maturity runs inversely to the complexity of the design task, less complex in digital circuits, higher in analog ones and still higher in radiofrequency circuits. Radiofrequency inductors are key culprits of such complexity. Their key performance parameters are inductance and quality factors, both a function of the frequency. The inductor optimization requires knowledge of such parameters at a few representative frequencies. Most common approaches for optimization-based radiofrequency circuit design use analytical models for the inductors. Although a lot of effort has been devoted to improve the accuracy of such analytical models, errors in inductance and quality factor in the range of 5%–25% are usual and it may go as high as 200% for some device sizes. When the analytical models are used in optimization-based circuit design approaches, these errors lead to suboptimal results, or, worse, to a disastrous non-fulfilment of specifications. Expert inductor designers rely on iterative evaluations with electromagnetic simulators, which, properly configured, are able to yield a highly accurate performance evaluation. Unfortunately, electromagnetic simulations typically take from some tens of seconds to a few hours, hampering their coupling to evolutionary computation algorithms. Therefore, analytical models and electromagnetic simulation represent extreme cases of the accuracy-efficiency trade-off in performance evaluation of radiofrequency inductors. Surrogate modeling strategies arise as promising candidates to improve such trade-off. However, obtaining the necessary accuracy is not that easy as inductance and quality factor at some representative frequencies must be obtained and both performances change abruptly around the self-resonance frequency, which is particular to each device and may be located above or below the frequencies of interest. Both, offline and online training methods will be considered in this work and a new two-step strategy for inductor modeling is proposed that significantly improves the accuracy of offline methods The new strategy is demonstrated and compared for both, single-objective and multi-objective optimization scenarios. Numerous experimental results show that the proposed two-step approach outperforms simpler application strategies of surrogate modelling techniques, getting comparable performances to approaches based on electromagnetic simulation but with orders of magnitude less computational effort. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents the thermal analysis results of integrated spiral inductors. Inductors, often used in analog integrated circuits for wireless applications, have very small dimensions, thus even a low power dissipation can give rise to elevated temperatures in circuits containing these elements. The thermal analysis is divided into two parts. First, the inductors thermal behavior is investigated using infrared thermography. Next, a theoretical model is developed and compared with the experimental measurements and numerical simulations. [Copyright &y& Elsevier]

Abstract: This paper presents two techniques to reduce the area in the design of CMOS distributed amplifiers. The proposed techniques take into account the influence of compacting the layout and the use of stacked inductor for the artificial transmission lines on the distributed amplifier performance. Following these design guidelines, three prototypes have been fabricated in a low cost CMOS process. The measured gain is about 6dB with a cutoff frequency around 8GHz. The noise figure varies from 5 to 7dB and the circuits draw 30mA from a 3.3V voltage supply. With the developed area optimization design techniques, a maximum area reduction of 37% with respect to a conventional design has been achieved, without any significant performance degradation. [ABSTRACT FROM AUTHOR]

Abstract: In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20GHz. [Copyright &y& Elsevier]

In the last years, wireless LAN market has shown an incredible growth, exceeding expectations. This article presents a fully integrated LC voltage controlled oscillator in a low cost 0.35 μm BiCMOS process for the 5–6 GHz band, according to the IEEE 802.11a wireless LAN standard. The tank inductor has been designed by electromagnetic simulations. To test the VCO performance, a synthesizer for IEEE 802.11a has been designed. This work demonstrates the feasibility of a low cost silicon technology for the design of 5–6 GHz band circuits. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2632–2635, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23757 [ABSTRACT FROM AUTHOR]

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications. [ABSTRACT FROM AUTHOR]

Abstract: Ni0.4Cu0.2Zn0.4Fe2O4 thin films were fabricated on Si substrates by sol-gel method and rapid thermal annealing (RTA), their structural and magnetic properties were characterized using an X-diffraction, scanning electron microscopy (SEM), atomic force microscopy (AFM), and alternating gradient magnetometer (AGM). The experimental results show that sol-gel method can lower the crystallization temperature of the magnetic thin films effectively, which is beneficial to the realization of low temperature process of magnetic thin films. The thin films in the paper exhibit excellent soft magnetic performance. Finally, a micro inductor with integrated Ni0.4Cu0.2Zn0.4Fe2O4 thin film for RF ICs was fabricated and measured. The work shows that Ni0.4Cu0.2Zn0.4Fe2O4 thin films can be integrated into RF integrated inductors. [Copyright &y& Elsevier]

This paper presents an in-depth analysis of the operation of a CMOS single-chip three-dimensional inductor over a MOSFET structure at RF frequencies. Active circuitry is placed underneath the integrated inductors in order to take advantage of the vacant space. Measurements indicate that the operation of the MOSFET and of the inductor is affected in a predictable manner. The paper theoretically investigates the interaction between the two elements, analyzes the origin of all appearing effects and compares the theory with the experimental data from a typical CMOS process. Moreover, this study proposes possible applications and design guides and confirms the attractiveness of the inductor over MOSFET placement. [ABSTRACT FROM AUTHOR]

Printed circuit board (PCB) integrated inductors have been adapted for operation as fluxgate sensors. A ring core is made from an electrodeposited permalloy thin film and is sandwiched between the layers of the PCB. The sensor excitation winding is also integrated into the PCB design. The pick-up coil is wound around the frame of the PCB core. Different types of current excitation waveforms with tuned and nontuned pick-up coils were used. The achieved sensitivities for 60 turns of tuned/nontuned pick-up coil, a sinusoidal waveform excitation current of Irms=300 mA, and an excitation frequency of 150 kHz were 13100/1800 V/T. The achieved sensitivity for pulse excitation (Ipeak-peak=900 mA, Irms=184 mA, duty 20%) was 2100 V/T. Noise power density for pulse excitation was 1.2 nTrms/√Hz@1 Hz, noise rms value from 10 mHz to 10 Hz was 3.3 nT. A perming error of 1 μT was measured for a wide range of excitation currents. [ABSTRACT FROM PUBLISHER]

A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s. At a bit error rate of less than 10-12, it has a sensitivity of 20 mV. The transmitter comprises a clock multiplying unit and a multiplexer. The jitter of the transmitted data signal is 0.2 ps rms. This is facilitated by a novel notched inductor layout and a special power supply concept, which reduces cross-coupling between the transmitter and receiver. Integrated in a 0.13-μm CMOS technology, the total power consumption from both 1.2- and 2.5-V supplies is less than 1 W. [ABSTRACT FROM AUTHOR]

High-performance and small-size on-chip inductors play a critical role in contemporary radio-frequency integrated circuits. This work presents a reliable surrogate modeling technique combining low-fidelity EM simulation models, response surface approximations based on kriging interpolation, and space mapping technology. The reported method is useful for the development of broadband and highly accurate data-driven models of integrated inductors within a practical timeframe, especially in terms of the computational expense of training data acquisition. Application of the constructed surrogate model for rapid design optimization of a compact on-chip inductor is demonstrated. The optimized EM-validated design solution can be reached at a low computational cost, which is a considerable improvement over existing approaches. In addition, this work provides a description and illustrates the usefulness of a multi-fidelity design optimization method incorporating EM computational models of graduated complexity and local polynomial approximations managed by an output space mapping optimization framework. As shown by the application example, the final design solution is obtained at the cost of a few high-fidelity EM simulations of a small-size integrated coil. A supplementary description of variable-fidelity EM computational models and a trade-off between model accuracy and its processing time complements the work. [ABSTRACT FROM AUTHOR]

Three down-conversion mixers for low-voltage, balanced 900 MHz wireless applications are introduced. The mixers are implemented in a 0.8 μm BiCMOS process and based on the four transistor BJT switching quad widely used in Gilbert cells. The mixers are designed to operate at a supply voltage of 1.5 V and without external components. The implemented mixers have a few decibels of conversion loss, a third-order input intercept point of a few dBm and a single sideband noise figure of about 15 dB. It is demonstrated that modest mixer operation performance is achieved with a DC power consumption of only 1 mW. Also planar inductors on silicon and bond-wire inductors are shown to be valuable to achieve a return loss of about 9 dB for input and output ports of a mixer. The measurement results for the mixers as well as the lumped element models for the used planar inductor and for the bondwire are presented. [ABSTRACT FROM AUTHOR]

A 1.6 GHz fully monolithic silicon bipolar LC current-controlledoscillator (CCO) circuit implemented in a 0.8 µmBiCMOS technology and characterized for use in wireless applicationsis presented. The integrated resonator circuit uses high speed(18 GHz) bipolar transistors, a 14 nH rectangular spiral inductorfabricated by using a standard 2-level metallization, and a widebandpn-varactor structure. Additionally, to save chip area, the integratedcapacitors were fabricated below the planar inductor structure.In order to aid the IC design, a simple equivalent circuit modelfor the integrated inductor on silicon was developed and tested.The measured quiescent power dissipation of the integrated CCOcircuit is 1.9 mW to 5.5 mW from a supply of 2–;3 V, anda typical phase noise varies from −82 to −86 dBc/Hz at 100 kHz offset. [ABSTRACT FROM AUTHOR]

In this letter, a novel integrated power inductor with a vertical laminated NiFe magnetic core for improved inductance to resistance ratio (L/R) ratios is proposed and demonstrated. Both the windings and magnetic core are accommodated within a groove at the backside of a silicon substrate and connected to the front-side IC through vias for compactness. NiFe is used to increase the inductance, and vertical lamination is used to suppress the eddy current in the magnetic core and assist hard axis alignment. A 1- \mathrmmm^\mathbf 2 embedded inductor with 131-nH inductance and 60-m $\Omega $ dc resistance working in megahertz range is fabricated. The L/R ratio is increased by seven times compared with integrated inductors with similar area, making it suitable for portable electronics power conversion system-on-chip applications. [ABSTRACT FROM AUTHOR]

This letter presents a compact inductor model that is accurate beyond the inductor's self-resonance frequency. The inductor is represented as a short-circuited transmission line, whose impedance is a hyperbolic tangent function. This function is expanded to its third-order continued fractions approximation. The approximation results in a compact equivalent circuit model with frequency independent parameters that can be extracted directly from S-parameter measurements. No optimization is necessary in this process. The developed compact wideband inductor model is extremely useful for accurate transient and harmonic balance simulations where out of band response is important [ABSTRACT FROM PUBLISHER]

This letter presents the modeling of sub-nH radial patterned ground shield circular inductors fabricated in a silicon bipolar technology for radio frequency applications. Based on both electromagnetic simulations and experimental measurements, the well-known current sheet expression for circular spirals is revised and modified to improve its accuracy at lower inductance values. The proposed expression is also extended to inductors with polygonal geometries showing significant improvements with respect to the state-of-the-art. Finally, the original and modified expressions are employed in a lumped scalable model for silicon spiral inductors. Comparisons with measured data revealed that the modified expression allows error reductions as large as 20% with respect to the original one, on both inductance and quality factor simulations. [ABSTRACT FROM PUBLISHER]