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A high‐precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time‐to‐digital converter (TDC), is designed based on this high‐precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time interval. The TDC samples the two signals multiple times by a clock signal, whose period is shorter than that of the delay line. Consequently, the problem of limited resolution caused by a mismatch between delay lines in the delay‐line structure can be avoided, and the precision of the output can be improved. The proposed TDC is designed and simulated in Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm complementary metal–oxide–semiconductor process. Simulation results show that the differential non‐linearity and the integral non‐linearity are always less than one least significant bits. The proposed TDC achieves input dynamic range of 0–32.13 ns and time resolution of 9 ps. [ABSTRACT FROM AUTHOR]

In this study, the authors report on two different electronic interfaces for low‐power integrated circuits electric current monitoring through current‐to‐frequency (I–f) conversion schemes. This proposal displays the intrinsic advantages of the quasi‐digital systems regarding direct interfacing and self‐calibrating capabilities. In addition, as current‐sensing devices, they have made use of the giant magnetoresistance (GMR) technology because of its high sensitivity and compatibility with standard complementary metal oxide semiconductor processes. Single elements and Wheatstone bridges based on spin‐valves and magnetic tunnel junctions have been considered. In this sense, schematic‐level simulations for integration in Austria Microsystems 0.35 μm technology have been corroborated by means of experimental measurements with the help of printed circuit board prototypes and real GMR devices. Tables with relevant parameters (silicon area, power consumption, sensitivity etc.) have been constructed as practical tools for designers. Electric currents down to 2 μA have been resolved in this way. [ABSTRACT FROM AUTHOR]

This paper presents an economical time-domain CMOS smart temperature sensor with only one delay line. With the use of a path selection circuit, the delay line was used to first sense the temperature, to generate a pulse with a width proportional to absolute temperature (PTAT). The original delay line was then reused to measure the PTAT pulse. Final digital code conversion was fulfilled using a simple counter. Compared with former work with two delay lines, the proposed work with the novel structure can reduce one delay line to lower the circuit area. The proposed circuit was fabricated in a TSMC CMOS 0.35- μm 2P4M digital process, and had an extremely small chip area of 0.025 mm2, which is currently the best size among smart temperature sensors that has ever been reported when considering the CMOS process. The achieved measurement errors for eight chips are within -0.8°C-1.0 °C after two-point calibration over a 0 °C-100 °C temperature range. The effective resolution is measured to be 0.2 °C, and the power consumption is 1.5 μW at a sampling rate of 10 samples per second. [ABSTRACT FROM PUBLISHER]

A fully integrated near-infrared spectroscopy photoreceiver including two new silicon avalanche photodiodes (SiAPDs) and a new transimpedance amplifier (TIA) is proposed in this paper. SiAPDs are designed in p+/n-well structure with guard-rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise, low-power consumption, high gain-bandwidth product characteristics and it is robust against power-supply variation (1-3 V). This circuit is developed using 0.35 μm CMOS technology and the measurement results are compared with other results from the literature. The designed rectangular and octagonal SiAPDs have the avalanche gain of 100 and 45 with the breakdown voltage of 9 and 6 V and the photon absorption efficiency of 45% and 25% at 800 nm. Fabricated TIA offers high-transimpedance gain (up to 250 MV/A), tunable BW (1 kHz-1 GHz), extremely low input and output noises (100 fA/√Hz, 1.8 μV/√Hz), and low-power consumption (0.8 mW). The impact and effects of on-chip integration of SiAPD and TIA front-end have been also measured and evaluated. [ABSTRACT FROM PUBLISHER]

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to-digital converter fabricated in standard single poly six-metal 90-nm CMOS. [ABSTRACT FROM AUTHOR]

A very simple ring‐oscillator voltage‐controlled oscillator (VCO) structure for use in VCO‐ADC applications is presented. It has a greatly improved linearity compared with previously published VCOs. Measurement results of a 1 V, 65 nm CMOS prototype confirm the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

A W‐band 2.5 GHz bandwidth pulse generator comprising a voltage‐controlled oscillator (VCO) and a novel pulse former in a 65 nm CMOS technology is presented. The proposed sub‐harmonic pumped pulse former, which plays roles as both a frequency doubler and a pulse former, is designed to obtain high efficiency using a transformer‐based current reuse circuit. The VCO is implemented with a parallel combining transformer, which makes it insensitive to load variations due to pulse formation. Measurements show that the pulse generator achieves −1 dBm peak output power at 79 GHz. It can generate 800 ps pulse signals with an RF carrier of 76.1–79.6 GHz, achieving the energy cost rate of 50 pJ/pulse with a 1.25 GHz pulse repetition period. [ABSTRACT FROM AUTHOR]

3D-TCAD simulations in a 130-nm process are used to show the effect of guard rings and guard drains in mitigating charge collection and charge sharing between nodes. Experimental results quantifying the reduction in SET pulse width and the error cross section were obtained with the use of SET pulse width and SET error rate measurement test circuits fabricated in 130-nm and 180-nm processes. Results indicate that guard drains results in 30% lower error cross section compared to guard ring circuits. [ABSTRACT FROM PUBLISHER]

Most pulse width characterization circuits measure single-event transients (SETs) using a target circuit consisting of long inverter chains or temporal latches exposed to heavy-ions over extended periods of time. For these approaches, circuit-level effects eliminate shorter pulses due to prolonged heavy-ion exposure providing the worst case estimate of measurable transients. Simulation results in the IBM 180 nm and 90 nm technologies corroborate this effect and discuss the resulting factors affecting single event (SE) error cross-sections. Experimental evaluation of such a SET pulse width characterization circuit under heavy-ion exposure showed reduced number of events measured due to total dose effects as expected. Additional experimental and simulation results show that the length of the propagation chains in the target circuit (for capturing SETs), the exposed flux and time (total dose) affect the resulting number of SEs measured. [ABSTRACT FROM PUBLISHER]

Electrically programmable/writable fuses (e-fuses) with a Ni-silicided polycrystalline silicon narrow link and fabricated with four doping conditions were studied using two successive I-V measurements. The initial I-V sweeps can change e-fuses into targeted programmed states and display all of the programming processes where the currents change by many orders of magnitude. The second set of I-V curves can show stability and conduction in the programmed states for both bias polarities. Through the series of I-V measurements, the two-step programming with moderate blowing conditions could be reproduced and studied systematically. The programming processes of incompletely programmed states, before complete programming (CP), were found to be strongly dependent on the dopant conditions. The origin of the dopant dependency was considered within a simple electrical equivalent circuit model. At least two or three programmed states were identified among the completely programmed states in terms of the characteristic spreads of the final resistance and conduction behavior. The most distinctive currents after CP are similar to those in varistors. The stability of every programmed state is strongly dependent on the dopant conditions. [ABSTRACT FROM PUBLISHER]

This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit off currents under 1 pA while producing highest on currents. DC characteristics of the optimum n and p-channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2- and 3-input nand, nor, and xor gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 mum2 [ABSTRACT FROM PUBLISHER]

This paper reports the development of an in-field real- time successive jitter-measurement macro whose features include i-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; and 3) feedforward calibration, each of which helps attain high jitter-measurement resolution; as well as 4) an oversampling rate and measurement range-control technique. A test chip of the macro has been fabricated in a 90-nm process. It successfully measures small random jitter with 1-ps resolution, and large deterministic jitter can also be measured by extending the jitter-measurement range by a factor of 4. [ABSTRACT FROM AUTHOR]

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology [ABSTRACT FROM PUBLISHER]

Noise parameter measurements of submicrometer scaled-CMOS devices are error prone. These errors can propagate to a device model affecting the performance of low-noise amplifiers (LNAs) designed with them. In this paper, measurement errors in noise parameters of submicrometer scaled-CMOS devices are quantified. The sensitivity of different noise parameters to measurement and modeling errors is examined, showing that some parameters (NFmin,Rn) are more immune to such errors than others (Gopt,Bopt). We propose a modeling and design approach (desensitization by Rn-optimization) that can greatly alleviate the impact of such errors on the noise figure of LNAs. Measured results from a 90-nm LNA show substantial (ges 2.5 dB) improvement in its noise figure as a result of desensitization [ABSTRACT FROM PUBLISHER]

High accuracy radio-frequency (RF) measurements typically require a calibration to remove the undesired effects of the measurement apparatus. The calibration consists of measuring some combination of known standards such as short, open, load, through, and delay. When measurements are performed on-wafer for silicon RF integrated circuits (RFICs), a two-step calibration/de-embedding technique is typically used. First, the measurement system is calibrated to a reference plane located at the probe tips through measurement of calibration standards fabricated on an impedance-standard substrate. Second, on-wafer de-embedding standards are measured in an attempt to shift the reference plane to the terminals of the device under test (DUT). While significant effort has gone into the development of improved on-wafer de-embedding schemes, discrepancies between actual and de-embedded data still exist. In this article, we first discuss a specific case (a spiral inductor on silicon) for which there was a significant discrepancy between measurement and analysis. The problem is found to be with the measurement. This problem is detailed, and a technique we call "synthetic calibration" is described that can be used with any electromagnetic (EM) analysis to quantify calibration error for any proposed set of calibration standards. Due to the high expense and time required for wafer fabrication, it is important to successfully complete such a calibration validation prior to tape-out. [ABSTRACT FROM PUBLISHER]

Electron-beam testing technique includes photoemissive probing; electrooptic sampling; charge density probing and photoexcitation are analyzed. Among these techniques an ideal contactless probing system is simple, inexpensive to operate and compatible with the existing test equipment. It will not perturb the circuit and would measure electric signals with minimum crosstalk. Experimental results demonstrate that multiple optical test vectors can be input on the periphery of a DUT (device under test) with negligible crosstalk using this technique. The bandwidth of the test system would be compatible with picosecond data pulses and it would not be limited to certain materials. The approach offers increased testability and measurement of the "chip under test". [ABSTRACT FROM PUBLISHER]

The charging effect of an insulating specimen from electron beam (e-beam) irradiation may be utilized to facilitate imaging in the scanning electron microscope (SEM). This has been confirmed by a great deal of experimental work during the last three decades. Particularly, recent investigations indicate that even located underneath insulating thin films that a low energy e-beam cannot penetrate, conductors not biased and overlay marks, are observable through a novel imaging pattern, charging contrast. Unlike conventional SEM contrasts, which usually reflect surface characteristics, the dynamic charging contrast can reveal information of underlying structures without any external exciting signal. The authors consider that this kind of charging contrast arises from the different redistribution rates of secondary electrons returning to the surface under the surface local field of the charged specimen. The charging contrast has the prospect of extending the SEM application and forming new testing methods matched with the fast development of integrated circuits. [ABSTRACT FROM AUTHOR]

To establish a method for investigating hidden radiation sources and their mechanisms in a printed circuit board, we performed preliminary measurements of one-dimensional magnetic near-field distribution over pins of a large-scale integrated circuit (LSI) package by means of an optical method: the fiber-edge magnetooptic (FEMO) probing technique. The FEMO probe consists of fiber optics and a magnetooptic crystal glued at a fiber edge. Its planar spatial resolution is approximately 100 μm. It was found that a magnetic field generated from each LSI pin could be distinguished and some radiation was generated from ground and power supply lines. We compared the measured results with corresponding radiated electric field strength that was separately measured. The frequency of interest was the tenth harmonic of the output signal. We observed a strong correlation between those two experimental results, which suggests the effectiveness of our proposed method for near-field investigation. One of the beneficial features of the FEMO probe is its small probe head, due to which one can perform detailed near-field evaluations in a microscopic region. Furthermore, we tried to specify a major electromagnetic interference source by additional measurements of near-field distributions and frequency dependence of magnetooptic signals. It was suggested that the short-through current flowing in the power-supply system of the input/output circuits caused high-level radiated emission. [ABSTRACT FROM PUBLISHER]

ADCs have always been bottlenecks in electronic systems. Currently, ADCs are often integrated on a semiconductor substrate with other mixed-signal circuits. This creates a need for clever strategies for error measurement and correction. This paper describes an analytical method which allows implementation of the necessary test on-cell. The main requirement is to produce a high-quality sine wave on the board. The parameters of this effective resolution measurement procedure can be easily (in real time) accumulated by typical digital circuitry. [ABSTRACT FROM PUBLISHER]

A 0.6 μm BiCMOS interface for microelectromechanical systems (MEMS) based rotational accelerometers is presented. It is housed in an inexpensive standard SO-24 plastic package with a capacitive rotational accelerometer sensor produced using MEMS technology. This sensitive interface chip includes the analog-to-digital conversion, filtering, and interface functions. The analog-to-digital conversion is realized through a single-bit electromechanical Σ-Δ loop able to detect capacitive unbalancing as low as 50 aF (50×10-18 F). The produced bitstream is then processed by a digital chain and made available through a standard 3.3 V (5 V tolerant) three-wire serial bus. The signal bandwidth is about 800 Hz, the sensitivity is 2.5 rad/s2, with a full-scale sinewave of 200 rad/s2 and a signal-to-noise ratio peak of 38 dB over 30-800 Hz. Through the serial bus, it is also possible to program device characteristics including gain, offset, filter performance, and phase delay. The complete sensor is used in a feed-forward compensation scheme to cancel external disturbances acting on computer hard-disk drives so as to steadily keep the read-write heads on track: this allows greater track densities and better speed performance. [ABSTRACT FROM PUBLISHER]

Highly integrated ion-sensitive field-effect transistor (ISFET) microsystems require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip. This paper presents new ISFETs in standard CMOS, fabricated by post-processing of a standard CMOS VLSI chip. Unlike CMOS compatible ISFETs fabricated in a dedicated process, the new sensors are directly combined with state-of-the-art CMOS electronics and are subject to continuous technology upgrading. The ISFETs presented include an intermediate gate formed by one or more conducting layers placed between the gate oxide and the sensing layer. The combination of the highly isolating gate oxide of the MOS with a leaky or conducting sensing layer allows the use of low temperature materials that do not damage the CMOS chip. The operation of ISFETs with an intermediate gate and sensing layers fabricated at low temperature is modeled. ISFETs with a linear pH response and drift as low as 0.3 mV/h are reported. [ABSTRACT FROM PUBLISHER]

The performance of monolithically integrated metal-semiconductor-metal/high electron-mobility transistor (MSM/HEMT) and p-i-n/HEMT photoreceivers is reported. p-i-n/HEMT photoreceivers have been designed and fabricated, resulting in measured transimpedances of 700 Ω, an 8.3-GHz bandwidth, and measured sensitivities of -17.7 dBm at 10 Gb/s and -15.8 dBm at 12 Gb/s for a 231 - 1 pattern length pseudorandom bit sequence at a bit error rate of 10-9. Low-noise MSM-based pbotoreceivers have also been designed and fabricated, and frequency response, noise, and sensitivity measurements have been performed. Sensitivities of -16.9, -13.1, and -10.7 dBm were obtained at 5, 8, and 10 Gb/s, respectively. A direct comparison of p-i-n- and MSM-based photoreceivers is undertaken on photoreceivers with matched responsivity and bandwidth. Measurement and theoretical analysis of circuit and device noise indicates an anomalous sensitivity penalty in MSM-based receivers that arises due to intersymbol interference [ABSTRACT FROM PUBLISHER]

Quantifying the turn-on behavior of electrostatic discharge (ESD) protection devices under subnanosecond transients is critical to achieving robust protection against the Charged Device Model stress. A wafer-level very fast transmission-line pulse system (VFTLP) has been developed and is shown to successfully measure the turn-on time of a common ESD protection device. Both formal analysis and practical details regarding VFTLP system construction and operation are documented [ABSTRACT FROM PUBLISHER]

In this paper, we critically examine several important experimental aspects concerning ultrathin oxide reliability. The statistical nature of breakdown measurements and the impact on data interpretation is discussed. Thickness dependence of Weibull slopes and its impact on reliability projection is reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values. Within the framework of a general defect generation model, we explore the possibility of a voltage-dependent defect generation rate to account for the increase in voltage acceleration with decreasing voltages. Using direct experimental results, we clarify that strong temperature dependence found on ultrathin oxides is a voltage effect, not a thickness effect as previously suggested, In the context of voltage-dependent voltage acceleration, we experimentally resolve various seemingly contradicting and confusing observations such as temperature-independent voltage acceleration and non-Arrhenius temperature dependence found on ultrathin oxides. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domain constructed from two important empirical principles based on comprehensive experimental database [ABSTRACT FROM PUBLISHER]

Timing parameters of the standard cell library are essential for static timing analysis. An on‐chip picosecond resolution timing measurement system is presented. The system measures the rise/fall time of the signal and the setup/hold time of the flip flop. Compared with the SPICE simulation, the on‐chip physical measurement considerably improves the resolution of the timing parameters. [ABSTRACT FROM AUTHOR]

A pseudo‐cascode split‐transistor technique is proposed for DC‐gain enhancement of amplifiers in the subthreshold by exploiting the small size effects of metal–oxide semiconductor field effect transistors (MOSFETs) including the reverse short‐channel effect and the inverse narrow‐width effect. It requires no body‐biasing and occupies a small area. A compact 114 μm2 two‐stage amplifier with pseudo‐cascode compensation for in‐pixel amplification in vision sensors has been designed using the proposed technique. A total of 10 samples of split‐transistors and amplifiers fabricated in an UMC 0.18 μm standard CMOS process were measured. More than half of the tested split‐transistors show considerable DC‐gain enhancement over a wide range of bias currents and nine amplifiers have increased DC gains larger than 85 dB at about 4 nA power consumption. [ABSTRACT FROM AUTHOR]

A dual‐phase pulse‐modulated polar transmitter (PMPT) for wide power control range (PCR) applications is presented. For the validation of the proposed architecture, a radio‐frequency (RF) PMPT chip is implemented with a standard 0.18 μm 1P6M mixed‐signal CMOS process. The measurement results show that by using the proposed technique, wide PCR transmitters can be implemented accurately with low hardware requirements. An RF variable‐gain amplifier with just 21 dB of dynamic range is sufficient to pass the 80 dB PCR of the CDMA2000 standard. Compared with a conventional transmitter utilising linear power amplifiers, the proposed architecture has the potential of achieving much higher efficiency while being able to achieve chip‐level integration with eased circuit design specification. [ABSTRACT FROM AUTHOR]

A third‐order all‐pole analogue lowpass filter (LPF) with kHz‐to‐GHz bandwidth tunability is proposed. It embeds a current‐reuse active inductor into a current‐scalable source follower to realise three concurrently tunable poles in a single branch. The LPF fabricated in 0.18 μm CMOS measures a tunable − 3 dB cutoff from 0.8 kHz to 1.2 GHz, under a scalable power of 1.25 nW to 4.01 mW. Owing to no tuning capacitor, the die area is extremely compact (0.013 mm2) and the achieved filter efficiency is 0.52 to 1.11 pW/pole/Hz. [ABSTRACT FROM AUTHOR]

We report 1000-transistor-level monolithic circuit integration of sub-30-nm gate-recessed E/D GaN high-electron-mobility transistors with fT and fmax above 300 GHz. Simultaneous fT/fmax of 348/340 and 302/301 GHz for E- and D-mode devices, respectively, was measured, representing a 58% increase in fT compared with our previous report, due to improved management of RC parasitic delay. Three-terminal E- and D-mode breakdown voltage of 10.7 and 11.8 V, respectively, is limited by gate-drain breakdown. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) protection circuits are built into every pin of an integrated circuit (IC) to protect the core operating circuits. Many different standards groups have assumed the responsibility of producing ESD testing standards for the IC industry. The quality of ESD testing and their standards have suffered from a lack of measurement updates without an effort for periodic investigations of the real threat from ESD. Measurements to determine the real parameters of ESD threat have been ignored for too long. The present tests and standards will continue because organized ESD experts in standards groups are unconcerned with the real threat and can ignore the new data we have measured. [ABSTRACT FROM PUBLISHER]

On-chip microstrip transmission lines have been measured on-wafer from below 1 GHz up to 110 GHz. Using different pad de-embedding techniques as well as a technique based on two transmission lines of different length, the characteristic transmission line parameters have been accurately determined. The results are compared against simulation results from an electromagnetic full-wave solution and the parametric IBM model which is available in the technology's design kit. [ABSTRACT FROM PUBLISHER]

A 180-GHz monolithic sub-harmonic diode mixer is developed using 0.08-μm pseudomorphic InAlAs-InGaAs HEMT MMIC process on a 2-mil-thick InP substrate. This mixer demonstrates a conversion loss of better than 16.5 dB from 175 to 182 GHz with an LO drive of 13 dBm at 96 GHz. This is the first demonstration of a monolithic subharmonic HEMT diode mixer in this frequency range. The design and measurement of this monolithic microwave integrated circuit (MMIC) mixer and the waveguide-to-microstrip line transitions of the test-fixture are presented [ABSTRACT FROM PUBLISHER]

The authors present the results of two 160-190-GHz monolithic low-noise amplifiers (LNAs) fabricated with 0.07-μm pseudomorphic (PM) InAlAs-InGaAs-InP HEMT technology using a reactive ion etch (RIE) via hole process. A peak small signal gain of 9 dB was measured at 188 GHz for the first LNA with a 3 dB bandwidth from 164 to 192 GHz while the second LNA has achieved over 6 dB gain from 142 to 180 GHz. The same design (second LNA) was also fabricated with a 0.08-μm gate and a wet etch process, showing a small-signal gain of 6 dB with 6 dB noise figure. All the measurement results were obtained via on-wafer probing. The LNA noise measurement at 170 GHz is also the first attempt at this frequency [ABSTRACT FROM PUBLISHER]

A substrate coupling analysis flow is presented. The proposed method is fully compatible with the industry analogue/radio‐frequency design methodology, seamlessly integrates into the design environment, provides accurate estimation of the coupling effects and can model adequately all the mask design level isolation performance trends. Its accuracy is confirmed by correlating simulation results against on‐wafer silicon measurements in a 28 nm CMOS set of ring oscillators with a carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV, whereas the error sigma is 765 μV. [ABSTRACT FROM AUTHOR]