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The popular notion of Internet of Things (IoT) implies two salient features: 1. a diversity of small things, i.e., constrained devices; 2. their seamless integration with the Internet. Pioneering work in Wireless Sensor Networks (WSNs) have laid a solid technological foundation for autonomous, low power wireless communication among battery-powered, microcontroller-based devices. On the other hand, as devices are being connected to the Internet in large numbers, industry experts and regulators have associated IoT with enormous security risk. Sensitive personal information, highly complex business workflows, and critical infrastructure for public safety are at stake. In this dissertation, we first explore the scalability of IoT. Approaching from the particular angle of radio interference, we study unstable and faulty network behavior when links between low power radios are disrupted. Our low cost and practical interference generation tools fill a gap between protocol design and test. We then underline the threat of novel attacks at the physical layer, which lead to denial of service and battery draining of low power radios. Launched from low cost hardware, the attacks we devise are power-efficient and hard to detect; and they reach longer ranges than jamming. Finally, we take a step closer to realization of secure and large-scale IoT deployment by enabling certificate enrollment, a key component in a public key infrastructure, for small devices. We show that automated enrollment of device certificates becomes feasible when a memory and power efficient IoT protocol stack is leveraged. Spanning between the physical layer and the application layer, our work has enriched the knowledge domain of IoT and advanced the technological frontier of scalable and secure IoT deployment.

Wireless communication is a key enabler for connecting billions of Internet of Things devices. For networked embedded devices operating on limited energy resources, wireless communication dominates the power consumption. Moreover, as networked devices increasingly handle sensitive data, security concerns in wireless communication are continuously expanding. This dissertation develops novel solutions for low-power and secure wireless communication. Wireless transmitters consist of a series of steps, involving both analog and digital components, each playing a distinct role in the transmit chain. Conventional transmitters employ power-hungry analog components, leading to power consumption on the order of milliwatt. Backscatter transmitters significantly reduce communication power consumption to levels well below one milliwatt. This remarkable power efficiency is achieved by offloading power-hungry components to an external carrier emitter. However, backscatter transmitters encounter challenges in applications that demand medium to long communication range, because they rely heavily on powerful emitters in their proximity for an effective communication range. Instead of removing power-hungry components, our solution integrates the functions of these components into a low-power design. While still requiring an emitter, our transmitter does not reflect the carrier signal. Instead, we utilize a weak carrier signal to stabilize the transmitter, allowing a communication range of over one hundred meters even when the emitter is far away. This contribution takes a step forward in moving low-power communication beyond backscatter. Passive radiometric fingerprinting leverages imperfections of hardware components to identify and authenticate transmitters. Its passive nature fits well to secure low-power transmitters operating within constrained resources. To enhance the viability of radiometric fingerprinting, we make three contributions in this dissertation to facilitate its w

Deep Neural Networks (DNNs) are widely adopted to solve different problems ranging from speech recognition to image classification. DNNs demand a large amount of processing power, and their implementation on hardware, i.e., FPGA or ASIC, has received much attention. However, it is impossible to implement a DNN on hardware directly from its DNN descriptions, usually in Python language, libraries, and APIs. Therefore, it should be either implemented from scratch at Register Transfer Level (RTL), e.g., in VHDL or Verilog, or be transformed to a lower level implementation. One idea that has been recently considered is converting a DNN to C and then using High-Level Synthesis (HLS) to synthesize it on an FPGA. Nevertheless, there are various aspects to take into consideration during the transformation. In this thesis, we propose a multistage framework, DeepKit, that generates a synthesizable C implementation based on an input DNN architecture in a DNN description (Keras). Then, moving through the stages, various explorations and optimizations are performed with regard to accuracy, latency, resource utilization, and reliability. The framework is also implemented as a toolchain consisting of DeepHLS, AutoDeepHLS, DeepAxe, and DeepFlexiHLS, and results are provided for DNNs of various types and sizes.

This paper introduces the model of design (MoD), a framework that leverages category theory to study the design and development of computer-driven systems, to the academic and engineering communities dealing with computer systems. The model of design aims to offer a minimal framework for modelling the design and development of embedded computation across domains and abstractions, focusing on functional and extra-functional aspects as well as overarching concerns for automaticity, correctness and reuse. This nuanced approach provides insights into the theory and practice of computer systems design., QC 20231027

Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, these automation tools must also provide safety guarantees that aid or drive the certification processes. In line with this automation goal, We propose a novel design space exploration technique for the mapping functionality on IMA platforms. The design space exploration technique returns mappings of the functionality onto the platform that are safe and increasingly resource-efficient. A safe mapping is one where the functional and extra-functional requirements are met. A resource-efficient mapping is one where fewer processing elements are used to achieve a safe mapping. More importantly, the proposed technique can return computational proof that no safe mapping is likely possible. This proof is key for safety-critical contexts. To demonstrate the suitability of our technique for avionics systems design scenarios, we investigate its use with an industrial avionics case based on the ones from the PANORAMA ITEA3 project. The case study includes two avionics functionalities, one control functionality, and one streaming-like functionality. The platform is hierarchical and heterogeneous, with elements oriented for higher safety and elements oriented for higher performance. The avionics case-study evaluation shows that our novel design space exploration technique's abstractions and assumptions adequately represent avionics design scenarios directly or through a systematic overestimation. The technique is openly available within the design space exploration tool IDeSyDe. Therefore, designers can immediately benefit from the optimality and safety guar, Part of ISBN 979-835033357-2QC 20231215

Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, these automation tools must also provide safety guarantees that aid or drive the certification processes. In line with this automation goal, We propose a novel design space exploration technique for the mapping functionality on IMA platforms. The design space exploration technique returns mappings of the functionality onto the platform that are safe and increasingly resource-efficient. A safe mapping is one where the functional and extra-functional requirements are met. A resource-efficient mapping is one where fewer processing elements are used to achieve a safe mapping. More importantly, the proposed technique can return computational proof that no safe mapping is likely possible. This proof is key for safety-critical contexts. To demonstrate the suitability of our technique for avionics systems design scenarios, we investigate its use with an industrial avionics case based on the ones from the PANORAMA ITEA3 project. The case study includes two avionics functionalities, one control functionality, and one streaming-like functionality. The platform is hierarchical and heterogeneous, with elements oriented for higher safety and elements oriented for higher performance. The avionics case-study evaluation shows that our novel design space exploration technique's abstractions and assumptions adequately represent avionics design scenarios directly or through a systematic overestimation. The technique is openly available within the design space exploration tool IDeSyDe. Therefore, designers can immediately benefit from the optimality and safety guar, Part of ISBN 979-835033357-2QC 20231215

The UnoSat Platform is a software and 3D structure platform built with Arduino Uno boardsthat allows easier implementation of a satellite project in a 1-n unit CubeSat format. It isdesigned to improve and speed up development of balloon - nanosat projects of the M2 TSImaster. It provides a 3D-printable Lego based structure that can be extended by stackingmultiple pieces on top of each other. The structure parts allow to quickly increase thenumber of Arduinos and add shields on top of already integrated Arduinos. Because ofthis, the structure allows for easy prototyping, and printed pieces can be reused in futureprojects. The platform also provides a communication system that is very efficient andreduces the possibilities of programming mistakes when implementing communication. Itallows serializing and parsing data into and from a binary format, provides protection againsttransmission errors via cyclic redundancy checksum and allows dynamically sized messagepayloads. Additionally, it supports one way or both ways communication not only between agroundstation and an embedded device, but also between two embedded devices. The codeon the embedded device is generated specifically for a communication configuration, whichmakes it very efficient in terms of processing and memory usage on the embedded device.

Digital image correlation is a contactless optical method used for displacement and strain measurement which has become increasingly popular in the field of experimental mechanics. A specialized use case for the algorithm is to measure the clamping force in bolted joints, a crucial metric when considering the longevity and reliability of the constructs. However, in order to be able to measure the clamping force in real-time, the digital image correlation has to be carried out rapidly as the tightening of the bolts can happen in milliseconds. One approach to increase the speed of the process is hardware acceleration. This thesis presents and evaluates multiple variations of an Field Programmable Gate Arrays (FPGA)-accelerated digital image correlation framework. The goal of the project is to accelerate the image correlation to sufficient speeds so it can be used for highly dynamic and continuous tightenings, which can take 20 to 200 ms and 200 to 1000 ms or more to finish respectively. A baseline implementation was created based on an innovative digital image correlation framework. Strain calculation was altered for the specialized use of clamping force determination. Afterward, different parts of the framework were selected and optimized for hardware acceleration. The parts include both preprocessing and correlation steps. The targets for acceleration were optimized using techniques such as quantization and pipelining. The accelerators were created using high-level synthesis and the resulting implementations utilize both the processor and FPGA parts of a Zynq-7000 system-on-chip. Results show that all accelerators reduce the total execution time of the framework by varying degrees. Accelerators targeting the preprocessing parts such as Gaussian and B-spline filtering proved to be the most effective in speeding up the process achieving a 1,56 and 1,12 times speedup for the fixed-point and a 1,2 and 1,07 times speedup for the double floating-point versions respectivel, Digital image correlation(DIC) är en kontaktlös optisk metod, använd för mätning av förskjutning och töjning, som blivit en allt mer populär inom experimentell mekanik. Ett användningsområde för algoritmen är att mäta klämkraften i skruvförband, en avgörande faktor för hållbarhet och tillförlitlighet i konstruktioner. Men för att mäta klämkraft i realtid, behöver DIC utföras väldigt snabbt då åtdragningsförloppet kan ske inom loppet av millisekunder. En metod för att öka hastigheten är hårdvaruacceleration. Denna avhandling presenterar och utvärderar ett flertal varianter av ett Field Programmable Gate Arrays (FPGA)-accelererat DIC ramverk. Avhandlingen syftar till att accelerera bildkorrelationen tillräckligt mycket för att kunna användas till dynamiska och kontinuerliga åtdragningar som tar 20 till 200 ms respektive 200 till 1000 ms eller mer. En referens-implementation skapades baserat på ett innovativt DIC ramverk. Beräkning av töjning anpassades för specialfallet: bestämmandet av klämkraft. Efter det valdes olika delar av ramverket ut och optimerades för hårdvaruacceleration. De valda delarna innehåller både preprocessor- och korrelationssteg. Delarna som valdes ut för acceleration optimerades med hjälp av tekniker som kvantisering och pipelining. Acceleratorerna skapades med hjälp av high-level synthesis och de resulterande implementationerna använder både processor och FPGA i en Zynq-7000 system-on-chip. Resultaten visar att alla acceleratorer reducerar ramverkets totala exekveringstid med varierande grad. Acceleratorer som riktar sig mot preprocessing som Gaussian och B-spline filtrering visade sig vara mest effektiva och resulterade i en 1.56 respektive 1.12 gånger snabbare exekveringstid för fixed point, och 1.2 respektive 1.07 gånger snabbare exikveringstid för double floating-point. En kombinerad version som innehöll flera acceleratorer resulterade i en 1.9 gånger snabbare genomsnittlig exekveringstid. Slutsatsen är att den presenterade metoden inte är t

Generating random numbers can be accomplished through various methods, with the primary distinction lying between pseudo-random number generators (PRNGs), which are commonly used for applications that require a large amount of random data, and true random number generators (TRNGs), which are commonly used for applications that need security and unpredictability. This thesis explores the feasibility of harnessing frequency variations in the electrical grid as a source of entropy for a TRNG. By employing an iterative approach, the study has substantiated the likelihood that frequency fluctuations can serve as a reliable source of ran-domness for a TRNG. This assertion is supported by statistical testing using the comprehensive RNG testing suite known as DieHarder, where the final implementation of the TRNG yielded favourable outcomes. Nevertheless, it is worth noting that the artefact exhibited weaker resultson three specific tests within the suite, which can likely be attributed to a limited amount of generated data. Despite these limitations, the findings are undeniably promising, and futurere search endeavours should focus primarily on enhancing the generation speed of the TRNG. By doing so, it is anticipated that improved performance on the DieHarder suite and similar RNG testing suites can be achieved., Generering av slumptal kan åstadkommas mev hjälp av flera olika metoder. De två stora grupperna är pseudo-slumptalsgeneratorer (PRNG:er), som vanligtvis används för applikationer som kräver en stor mängd slumpmässiga data, och sanna slumptalsgeneratorer (TRNG:er), som ofta används för applikationer som behöver säkerhet och oförutsägbarhet. Detta examensarbete undersöker möjligheten att utnyttja frekvensvariationer i det elektriska nätetverket som en källa till entropi för en TRNG. Genom att använda ett iterativt tillvägagångssätt har studien underbyggt sannolikheten att frekvensfluktuationer kan fungera som en pålitlig källa till slumpmässighet för en TRNG. Detta påstående stöds av statistiska tester med den omfattande RNG-testsviten känd som DieHarder, där den slutliga implementeringen av TRNG:n gav gynnsamma resultat. Det är värt att notera att artefacten visade svagare resultat på tre specifika tester inom sviten, vilket sannolikt kan tillskrivas en begränsad mängd genererad data. Trots dessa begränsningar är resultaten onekligen lovande, och framtida forskningsansträngningar bör främst fokusera på att öka generationshastigheten för generatorn. Genom att göra det förväntas det att bättre resultat från DieHarder och liknande RNG-testsviter kan uppnås.

This thesis investigates anomaly detection and classification in a simulated modular manufacturingenvironment using Machine Learning algorithm Random Forest. This algorithm is tested on a localcomputer and an embedded device, specifically the Raspberry PI. The performance of Random Forestmodels is evaluated for anomaly detection and classification tasks, considering different evaluationmetrics and execution time. The results indicate variations in model performance across differentmodules and classification tasks. It is observed that the limited computing resources of the RaspberryPI for anomaly detection tasks lead to significantly higher prediction times compared to a computer,highlighting the impact of embedded systems’ constraints on ML model execution

The safety requirements are often described via specifications called contracts. To verify that the system fulfills certain safety requirements, for instance, in the assume-guarantee contract specification, the key safety indicators are organized, so that if certain assumptions hold then the respective behaviour is guaranteed. Safety contracts provide a means of exposing potential incompatibilities early in the development process, selecting components to reuse, certifying systems, and identifying uncertainty sources during the operational phase. There exist several studies on contract-based safety assurance, however, there is not any systematic study in this field. For this, a first Systematic Literature Review (SLR) is carried out to obtain an overview of the various contract-based safety assurance concepts, problems, proposed solutions, and their usefulness. In our study, the identification and selection of the primary studies were based on a well-planned search strategy. The search process identified a total of 2881 studies published between 1969 and 2021, out of which 66 studies were selected through a multi-stage process according to our predefined SLR protocol. This SLR aims to highlight the state-of-the-art of contract-based safety assurance and identify potential gaps for future research. Based on research topics in selected studies, we identified the following main categories: contract type, analysis techniques for system safety, compliance with standards, development stage, domain, level of automation, type of study and evaluation, and tool support. The findings of the systematic review not only highlight that the contracts are even more important for advanced safety-critical systems but also strategies to exploit their full potential should be considered in future studies. The suggestions revealed for future research include the usage of contracts for adapting new behaviour, defining system boundaries, interacting with other systems, managing risk during

Reliability concerns of embedded systems are traditionally resolved by software-based control flow checking (CFC) methods where the execution flow of the processor is monitored to detect and compensate flow violations. Traditional CFC methods may lose their efficiency when it comes to multiprocessing embedded systems. In this paper, we introduce and validate a novel flow error model for multiprocessing embedded systems. Further, we propose a holistic CFC system which performs the flow checking of the processes of interest. The proposed CFC checking introduces the concept of a single monitoring process intended to check the execution flow of as many processes as wanted within an multiprocessing embedded system. Proposed solution does not introduce any substantial overheads in performance and memory consumption. Even more important is method's insensitivity to the number of checked processes. Our wide evaluations show the average performance overhead of 13.77%, average code-size overhead of 51.71%, and the average memory overhead of 1.95% on the Mibench benchmark suite. Results of fault injections confirm that the proposed CFC method successfully detects more than 95% of flow errors including our newly defined error model. © 2023 IEEE.

To solve problems related to Radio Frequency Identification, as well as to develop new technologies and applications with chipless RFID tags, this article describes the development of an innovative reader system based on Software-Defined Radios. Called SpuR, the system proposes a method of reading the spectral signature of RFID tags chipless, using general purpose hardware, reconfigurable by software, and operating in a wide frequency range without the need to change the reading equipment. This approach allows the accurate reading and identification of different types of chipless tags, using a classification procedure, by Euclidean distance, comparing them with a previously stored database.

Modern embedded platforms need sophisticated resource managers to utilize their heterogeneous computational resources efficiently. Furthermore, such platforms are subject to fluctuating workloads that are unforeseeable at design time. Predicting the incoming workload could enhance the efficiency of resource management in this situation. But is that the case? And, if so, how substantial is this improvement? Does multiple-step-ahead prediction of the workload contribute to this improvement? How precise must the prediction be to improve decisions rather than cause harm? By proposing a prediction-based resource manager that aims at meeting task deadlines while minimizing energy usage, and by conducting extensive tests, we attempt to provide answers to the aforementioned questions., Funding: Swedish Foundation for Strategic Research (SSF) [FUS21-0033]

Flexible wearable sensor electronics, combined with advanced software functions, pave the way toward increasingly intelligent healthcare devices. One important application area is limb prosthesis, where printed flexible sensor solutions enable efficient monitoring and assessing of the actual intra-socket dynamic operation conditions in clinical and other more natural environments. However, the data collected by such sensors suffer from variations and errors, leading to difficulty in perceiving the actual operational conditions. This paper proposes a novel method for detecting anomalies in the data that are collected for measuring the intra-socket dynamic operation conditions by printed flexible wearable sensors. A discrete generative model based on Variational AutoEncoder (VAE) is used first to encode the collected multi-variant time-series data in terms of latent states. After that, a clustering method based on the Self-Organizing Map (SOM) is used to acquire discrete and interpretable representations of the VAE encoded latent states. An adaptive Markov chain is utilized to detect anomalies by quantifying state transitions and revealing temporal dependencies. The contributions of the proposed architecture conclude as follows: (1) Using the VAE-SOM hybrid model to regularize the continues data as discrete states, supporting interpreting the operational data to analytic models. (2) Employing adaptive Markov chains to generalize the transitions of these states, allowing to model the complex operational conditions. Compared with benchmark methods, our architecture is validated via two public datasets and achieves the best F1 scores. Moreover, we measure the run-time performance of this lightweight architecture. The results indicate that the proposed method performs low computational complexity, facilitating the applications on real-life productions., Funding Agencies|Socket-Sense - European Union [825429]; National Natural Science Foundation of China [62011530132]; (NSFC-STINT project) [62076066]; Shanghai Municipal Science and Technology Major Project [2021SHZDZX0103]

Deep Neural Networks (DNNs) are widely adopted to solve different problems ranging from speech recognition to image classification. DNNs demand a large amount of processing power, and their implementation on hardware, i.e., FPGA or ASIC, has received much attention. However, it is impossible to implement a DNN on hardware directly from its DNN descriptions, usually in Python language, libraries, and APIs. Therefore, it should be either implemented from scratch at Register Transfer Level (RTL), e.g., in VHDL or Verilog, or be transformed to a lower level implementation. One idea that has been recently considered is converting a DNN to C and then using High-Level Synthesis (HLS) to synthesize it on an FPGA. Nevertheless, there are various aspects to take into consideration during the transformation. In this thesis, we propose a multistage framework, DeepKit, that generates a synthesizable C implementation based on an input DNN architecture in a DNN description (Keras). Then, moving through the stages, various explorations and optimizations are performed with regard to accuracy, latency, resource utilization, and reliability. The framework is also implemented as a toolchain consisting of DeepHLS, AutoDeepHLS, DeepAxe, and DeepFlexiHLS, and results are provided for DNNs of various types and sizes.

The integration of control systems with wireless communication networks has gainedsignificant popularity, leading to the emergence of wireless networked control systems(WNCS). WNCS comprises wireless devices such as sensors, actuators, andcontrollers that work together to ensure system stabilizability. However, communicationamong these wireless devices often relies on relay nodes, which presents a challengein guaranteeing system stabilizability due to potential failures caused by natural eventsor malicious activities targeting and disabling these nodes. This study proposes an approach to enhance the resilience of wireless sensor networks(WSNs) utilizing the WirelessHART communication protocol. The objective is to designthe WSNs and controller that can ensure stabilizability, even in the specific number ofrelay node failures. The study employs two key methodologies: firstly, the analysis ofconditions such as controllability, observability, solvability of fault detection andisolation, and the associated requirements to guarantee system stabilizability. Secondly,MATLAB simulations are employed to test the proposed system. By combiningtheoretical analysis and practical simulations, the study provides valuable insights anddesign strategies that contribute to the advancement of WNCS, enabling their reliabilityand stability in the face of potential relay node failures., Integrationen av styrsystem med trådlösa kommunikationsnätverk har blivit mycketpopulär, vilket har lett till framväxten av trådlösa nätverksstyrningssystem (WNCS).WNCS omfattar trådlösa enheter som sensorer, aktuatorer och styrenheter som arbetartillsammans för att säkerställa systemets stabilisering. Kommunikationen mellan dessatrådlösa enheter förlitar sig emellertid ofta på relänoder, vilket utgör en utmaning föratt garantera systemets stabilisering på grund av potentiella fel orsakade av naturligahändelser eller skadliga aktiviteter som riktar sig mot och inaktiverar dessa noder. Denna studie föreslår ett tillvägagångssätt för att förbättra motståndskraften hos trådlösasensornätverk (WSNs) med hjälp av kommunikationsprotokollet WirelessHART. Måletär att utforma WSN och styrenheter som kan säkerställa stabilisering även vid ettspecifikt antal relänodfel. Studien använder sig av två huvudsakliga metoder: för detförsta analys av villkor såsom styrbarket, observerbarheten, lösbarheten hos felupptäcktoch isolering metod och de tillhörande kraven för att garantera systemets stabilisering.För det andra används MATLAB-simuleringar för att testa det föreslagna systemet.Genom att kombinera teoretisk analys och praktiska simuleringar ger studien värdefullainsikter och designstrategier som bidrar till framsteg inom WNCS, vilket möjliggörtillförlitlighet och stabilitet även vid potentiella fel på relänoder.

Compilers, complex programs with the potential to greatly facilitate software and hardware design. This thesis focuses on enhancing the Spade hardware description language, known for its user-friendly approach to hardware design. In the realm of hardware development data size - for numerical values data size is known as "wordlength" - plays a critical role for reducing the hardware resources. This study presents an innovative approach that seamlessly integrates wordlength inference directly into the Spade language, enabling the over-estimation of numeric data sizes solely from the program's source code. The methodology involves iterative development, incorporating various smaller implementations and evaluations, reminiscent of an agile approach. To assess the efficacy of the wordlength inference, multiple place and route operations are performed on identical Spade code using various versions of nextpnr. Surprisingly, no discernible impact on hardware resource utilization emerges from the modifications introduced in this thesis. Nonetheless, the true significance of this endeavor lies in its potential to unlock more advanced language features within the Spade compiler. It is important to note that while the wordlength inference proposed in this thesis shows promise, it necessitates further integration efforts to realize its full potential.

Deep Neural Networks (DNNs) are widely adopted to solve different problems ranging from speech recognition to image classification. DNNs demand a large amount of processing power, and their implementation on hardware, i.e., FPGA or ASIC, has received much attention. However, it is impossible to implement a DNN on hardware directly from its DNN descriptions, usually in Python language, libraries, and APIs. Therefore, it should be either implemented from scratch at Register Transfer Level (RTL), e.g., in VHDL or Verilog, or be transformed to a lower level implementation. One idea that has been recently considered is converting a DNN to C and then using High-Level Synthesis (HLS) to synthesize it on an FPGA. Nevertheless, there are various aspects to take into consideration during the transformation. In this thesis, we propose a multistage framework, DeepKit, that generates a synthesizable C implementation based on an input DNN architecture in a DNN description (Keras). Then, moving through the stages, various explorations and optimizations are performed with regard to accuracy, latency, resource utilization, and reliability. The framework is also implemented as a toolchain consisting of DeepHLS, AutoDeepHLS, DeepAxe, and DeepFlexiHLS, and results are provided for DNNs of various types and sizes.

We present NeRTA (Next Release Time Analysis), a technique to enable dynamic software updates for low-level control software of mobile robots. Dynamic software updates enable software correction and evolution during system operation. In mobile robotics, they are crucial to resolve software defects without interrupting system operation or to enable on-the-fly extensions. Low-level control software for mobile robots, however, is time sensitive and runs on resource-constrained hardware with no operating system support. To minimize the impact of the update process, NeRTA safely schedules updates during times when the computing unit would otherwise be idle. It does so by utilizing information from the existing scheduling algorithm without impacting its operation. As such, NeRTA works orthogonal to the existing scheduler, retaining the existing platform-specific optimizations and fine-tuning, and may simply operate as a plug-in component. To enable larger dynamic updates, we further conceive an additional mechanism called bounded reactive control and apply mixed-criticality concepts. The former cautiously reduces the overall control frequency, whereas the latter excludes less critical tasks from NeRTA processing. Their use increases the available idle times. We combine real-world experiments on embedded hardware with simulations to evaluate NeRTA. Our experimental evaluation shows that the difference between NeRTA’s estimated idle times and the measured idle times is less than 15% in more than three-quarters of the samples. The combined effect of bounded reactive control and mixed-criticality concepts results in a 150+% increase in available idle times. We also show that the processing overhead of NeRTA and of the additional mechanisms is essentially negligible., UPDATE

Wireless communication is a key enabler for connecting billions of Internet of Things devices. For networked embedded devices operating on limited energy resources, wireless communication dominates the power consumption. Moreover, as networked devices increasingly handle sensitive data, security concerns in wireless communication are continuously expanding. This dissertation develops novel solutions for low-power and secure wireless communication. Wireless transmitters consist of a series of steps, involving both analog and digital components, each playing a distinct role in the transmit chain. Conventional transmitters employ power-hungry analog components, leading to power consumption on the order of milliwatt. Backscatter transmitters significantly reduce communication power consumption to levels well below one milliwatt. This remarkable power efficiency is achieved by offloading power-hungry components to an external carrier emitter. However, backscatter transmitters encounter challenges in applications that demand medium to long communication range, because they rely heavily on powerful emitters in their proximity for an effective communication range. Instead of removing power-hungry components, our solution integrates the functions of these components into a low-power design. While still requiring an emitter, our transmitter does not reflect the carrier signal. Instead, we utilize a weak carrier signal to stabilize the transmitter, allowing a communication range of over one hundred meters even when the emitter is far away. This contribution takes a step forward in moving low-power communication beyond backscatter. Passive radiometric fingerprinting leverages imperfections of hardware components to identify and authenticate transmitters. Its passive nature fits well to secure low-power transmitters operating within constrained resources. To enhance the viability of radiometric fingerprinting, we make three contributions in this dissertation to facilitate its w

The popular notion of Internet of Things (IoT) implies two salient features: 1. a diversity of small things, i.e., constrained devices; 2. their seamless integration with the Internet. Pioneering work in Wireless Sensor Networks (WSNs) have laid a solid technological foundation for autonomous, low power wireless communication among battery-powered, microcontroller-based devices. On the other hand, as devices are being connected to the Internet in large numbers, industry experts and regulators have associated IoT with enormous security risk. Sensitive personal information, highly complex business workflows, and critical infrastructure for public safety are at stake. In this dissertation, we first explore the scalability of IoT. Approaching from the particular angle of radio interference, we study unstable and faulty network behavior when links between low power radios are disrupted. Our low cost and practical interference generation tools fill a gap between protocol design and test. We then underline the threat of novel attacks at the physical layer, which lead to denial of service and battery draining of low power radios. Launched from low cost hardware, the attacks we devise are power-efficient and hard to detect; and they reach longer ranges than jamming. Finally, we take a step closer to realization of secure and large-scale IoT deployment by enabling certificate enrollment, a key component in a public key infrastructure, for small devices. We show that automated enrollment of device certificates becomes feasible when a memory and power efficient IoT protocol stack is leveraged. Spanning between the physical layer and the application layer, our work has enriched the knowledge domain of IoT and advanced the technological frontier of scalable and secure IoT deployment.

Precision livestock farming allows farmers to optimize herd management while significantly reducing labor needs. Individualized monitoring of cattle feeding behavior offers valuable data to assess animal performance and provides valuable insights into animal welfare. Current acoustic foraging activity recognizers achieve high recognition rates operating on computers. However, their implementations on portable embedded systems (for use on farms) need further investigation. This work presents two embedded deployments of a state-of-the-art foraging activity recognizer on a low-power ARM Cortex-M0+ microcontroller. The parameters of the algorithm were optimized to reduce power consumption. The embedded algorithm processes masticatory sounds in real-time and uses machine-learning techniques to identify grazing, rumination and other activities. The overall classification performance of the two embedded deployments achieves an 84% and 89% balanced accuracy with a mean power consumption of 1.8 mW and 12.7 mW, respectively. These results will allow this deployment to be integrated into a self-powered acoustic sensor with wireless communication to operate autonomously on cattle.

We present NeRTA (Next Release Time Analysis), a technique to enable dynamic software updates for low-level control software of mobile robots. Dynamic software updates enable software correction and evolution during system operation. In mobile robotics, they are crucial to resolve software defects without interrupting system operation or to enable on-the-fly extensions. Low-level control software for mobile robots, however, is time sensitive and runs on resource-constrained hardware with no operating system support. To minimize the impact of the update process, NeRTA safely schedules updates during times when the computing unit would otherwise be idle. It does so by utilizing information from the existing scheduling algorithm without impacting its operation. As such, NeRTA works orthogonal to the existing scheduler, retaining the existing platform-specific optimizations and fine-tuning, and may simply operate as a plug-in component. To enable larger dynamic updates, we further conceive an additional mechanism called bounded reactive control and apply mixed-criticality concepts. The former cautiously reduces the overall control frequency, whereas the latter excludes less critical tasks from NeRTA processing. Their use increases the available idle times. We combine real-world experiments on embedded hardware with simulations to evaluate NeRTA. Our experimental evaluation shows that the difference between NeRTA’s estimated idle times and the measured idle times is less than 15% in more than three-quarters of the samples. The combined effect of bounded reactive control and mixed-criticality concepts results in a 150+% increase in available idle times. We also show that the processing overhead of NeRTA and of the additional mechanisms is essentially negligible., UPDATE

Wireless communication is a key enabler for connecting billions of Internet of Things devices. For networked embedded devices operating on limited energy resources, wireless communication dominates the power consumption. Moreover, as networked devices increasingly handle sensitive data, security concerns in wireless communication are continuously expanding. This dissertation develops novel solutions for low-power and secure wireless communication. Wireless transmitters consist of a series of steps, involving both analog and digital components, each playing a distinct role in the transmit chain. Conventional transmitters employ power-hungry analog components, leading to power consumption on the order of milliwatt. Backscatter transmitters significantly reduce communication power consumption to levels well below one milliwatt. This remarkable power efficiency is achieved by offloading power-hungry components to an external carrier emitter. However, backscatter transmitters encounter challenges in applications that demand medium to long communication range, because they rely heavily on powerful emitters in their proximity for an effective communication range. Instead of removing power-hungry components, our solution integrates the functions of these components into a low-power design. While still requiring an emitter, our transmitter does not reflect the carrier signal. Instead, we utilize a weak carrier signal to stabilize the transmitter, allowing a communication range of over one hundred meters even when the emitter is far away. This contribution takes a step forward in moving low-power communication beyond backscatter. Passive radiometric fingerprinting leverages imperfections of hardware components to identify and authenticate transmitters. Its passive nature fits well to secure low-power transmitters operating within constrained resources. To enhance the viability of radiometric fingerprinting, we make three contributions in this dissertation to facilitate its w

The popular notion of Internet of Things (IoT) implies two salient features: 1. a diversity of small things, i.e., constrained devices; 2. their seamless integration with the Internet. Pioneering work in Wireless Sensor Networks (WSNs) have laid a solid technological foundation for autonomous, low power wireless communication among battery-powered, microcontroller-based devices. On the other hand, as devices are being connected to the Internet in large numbers, industry experts and regulators have associated IoT with enormous security risk. Sensitive personal information, highly complex business workflows, and critical infrastructure for public safety are at stake. In this dissertation, we first explore the scalability of IoT. Approaching from the particular angle of radio interference, we study unstable and faulty network behavior when links between low power radios are disrupted. Our low cost and practical interference generation tools fill a gap between protocol design and test. We then underline the threat of novel attacks at the physical layer, which lead to denial of service and battery draining of low power radios. Launched from low cost hardware, the attacks we devise are power-efficient and hard to detect; and they reach longer ranges than jamming. Finally, we take a step closer to realization of secure and large-scale IoT deployment by enabling certificate enrollment, a key component in a public key infrastructure, for small devices. We show that automated enrollment of device certificates becomes feasible when a memory and power efficient IoT protocol stack is leveraged. Spanning between the physical layer and the application layer, our work has enriched the knowledge domain of IoT and advanced the technological frontier of scalable and secure IoT deployment.

This paper introduces the model of design (MoD), a framework that leverages category theory to study the design and development of computer-driven systems, to the academic and engineering communities dealing with computer systems. The model of design aims to offer a minimal framework for modelling the design and development of embedded computation across domains and abstractions, focusing on functional and extra-functional aspects as well as overarching concerns for automaticity, correctness and reuse. This nuanced approach provides insights into the theory and practice of computer systems design., QC 20231027

Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, these automation tools must also provide safety guarantees that aid or drive the certification processes. In line with this automation goal, We propose a novel design space exploration technique for the mapping functionality on IMA platforms. The design space exploration technique returns mappings of the functionality onto the platform that are safe and increasingly resource-efficient. A safe mapping is one where the functional and extra-functional requirements are met. A resource-efficient mapping is one where fewer processing elements are used to achieve a safe mapping. More importantly, the proposed technique can return computational proof that no safe mapping is likely possible. This proof is key for safety-critical contexts. To demonstrate the suitability of our technique for avionics systems design scenarios, we investigate its use with an industrial avionics case based on the ones from the PANORAMA ITEA3 project. The case study includes two avionics functionalities, one control functionality, and one streaming-like functionality. The platform is hierarchical and heterogeneous, with elements oriented for higher safety and elements oriented for higher performance. The avionics case-study evaluation shows that our novel design space exploration technique's abstractions and assumptions adequately represent avionics design scenarios directly or through a systematic overestimation. The technique is openly available within the design space exploration tool IDeSyDe. Therefore, designers can immediately benefit from the optimality and safety guar, QC 20231025

In today’s global and aggressive market system, for manufacturing companies to remain competitive, they must manufacture high-quality products that can be produced at a low cost; they also must respond efficiently to customers’ predictable and unpredictable needs and demand variations. Increasingly shortened product lifecycles, as well as product customization degrees, lead to swift changes in the market that need to be supported by capable and flexible resources able to produce faster and deliver to the market in shorter periods while maintaining a high degree of cost-efficiency. To cope with all these challenges, the setup of production systems needs to shift toward Reconfigurable Manufacturing Systems (RMSs), making production capable of rapidly and economically changing its functionality and capacity to face uncertainties, such as unforeseen market variations and product changes. Despite the advantages of RMSs, designing and managing these systems to achieve a high-efficiency level is a complex and challenging task that requires optimization techniques. Simulation-based optimization (SBO) methods have been proven to improve complex manufacturing systems that are affected by predictable and unpredictable events. However, the use of SBO methods to tackle challenging RMS design and management processes is underdeveloped and rarely involves Multi-Objective Optimization (MOO). Only a few attempts have applied Simulation-Based Multi-Objective Optimization (SMO) to simultaneously deal with multiple conflictive objectives. Furthermore, due to the intrinsic complexity of RMSs, manufacturing organizations that embrace this type of system struggle with areas such as system configuration, number of resources, and task assignment. Therefore, this dissertation contributes to such areas by employing SMO to investigate the design and management of RMSs. The benefits for decision-makers have been demonstrated when SMO is employed toward RMS-related challenges. These benefits hav, I dagens globala och högst föränderliga marknad för att vara konkurrenskraftig måste tillverkandebolag producera högkvalitativa produkter som produceras till låga kostnader och möter kunders behov samt är anpassningsbara till marknadens variationer i efterfrågan. De allt kortare produktlivscyklerna och graden av produktanpassning leder till snabba förändringar på marknaden som behöver stödjas av mer kapabla och flexibla produktionsresurser som ökar produktionstakten och leverera till marknaden på kortare tid med bibehållen hög kostnadseffektivitet. För att hantera en sådan utmaning måste produktionssystemens uppbyggnad skifta mot omkonfigurerbara tillverkningssystem (RMS), vilket möjliggör för produktionen att på ett snabbt och kostnadseffektivt sätt ändra sin funktion och kapacitet för att möta oförutsedda marknadsvariationer och produktförändringar. Trots de fördelar som RMS för med sig så är design och nyttjande av dessa system för med en hög effektivitetsgrad en komplex och utmanande uppgift som kräver användning av optimeringstekniker. Metoder för simuleringsbaserad optimering (SBO) har visat sig förbättra komplexa tillverkningssystem som utsätts för planerade och oplanerade händelser. Användningen av SBO-metoder för att ta itu med utmaningen rörande design och effektiv nyttjande av RMS är dock underutvecklad och där nyttjande av flermålsoptimering (MOO) är begränsad. Det har endast skett ett fåtal försök att tillämpa simulering baserad flermålsoptimering (SMO) för att hantera flera konflikterande mål. På grund av den komplexet i RMS kämpar tillverkningsorganisationer som om-famnar den här typen av system med områden som systemkonfiguration, antal resurser och uppgiftstilldelning. Följaktligen bidrar denna avhandling till de nämnda områdena genom att använda SMO för att undersöka designen och hanteringen av RMS. Fördelarna för beslutsfattare har visat sig när SMO används mot RMS-utmaningarna. Dessa fördelar har förbättrats genom att kombinera SMO med kunskapsup

Video is the most used tool for sport performance analysis as it provides a common reference point for the coach and the athlete. The problem with video is that it is a subjective tool. To overcome this, motion capture systems can used to get an objective 3D model of a per- son’s posture and motion, but only in laboratory settings. Unfortunately, many activities, such as most outdoor sports, cannot be captured in a lab without compromising the activity. In this paper, we propose to use an aerial drone system equipped with depth cameras, AI-based marker- less motion capture software to perform automatic skeleton tracking and real-time sports performance analysis of athletes. We experiment with off-the-shelf drone systems, miniaturized depth cameras, and commer- cially available skeleton tracking software to build a system for analyzing sports-related performance of athletes in their real settings. To make this a fully working system, we have conducted a few initial experiments and identified many issues that still needs to be addressed., Part of proceedings ISBN 978-3-031-35893-7 978-3-031-35894-4QC 20230818, My Digital Drone Twin

Nanoconstriction spin-Hall nano-oscillators (NC-SHNOs) are excellent devices for a wide variety of applications, from RF communication to bio-inspired computing. NC-SHNOs are easy to fabricate in large arrays, are CMOS compatible, and feature a narrow linewidth and high output power. However, in order to take full advantage of the device capabilities, a systematic analysis of the array behavior with respect to the number and dimensions of oscillators, the temperature of operation, and the influence of layer quality is needed. Here, we focus on micromagnetic simulations of 2 x 2 and 4 x 4 NC-SHNO arrays with single oscillators separated by up to 300 nm. We observe a synchronization scheme that allows for column-wise selection of the oscillation frequency for a larger pitch. However, for smaller pitches, a coherent oscillation volume was observed, and this volume included both the constrictions and extended beyond that region. A local variation in the exchange coupling in the active oscillator region was investigated by placing physical grains in the free magnetic layer, and it was shown to influence both the stable current range and the resulting frequency and output power. De-coupling the oscillators along rows or columns could provide higher power due to more favorable phase shifts between oscillators. Our investigation helps in achieving a deeper understanding of the intrinsic working principles of NC-SHNO arrays and how they reach fully synchronized states, and this will help to expand non-conventional computing capabilities., QC 20230620

Today digital revolution is having a dramatic impact on the pharmaceutical industry and the entire healthcare system. The implementation of machine learning, extreme-scale computer simulations, and big data analytics in the drug design and development process offers an excellent opportunity to lower the risk of investment and reduce the time to the patient. Within the LIGATE project 1, we aim to integrate, extend, and co-design best-in-class European components to design Computer-Aided Drug Design (CADD) solutions exploiting today's high-end supercomputers and tomorrow's Exascale resources, fostering European competitiveness in the field. The proposed LIGATE solution is a fully integrated workflow that enables to deliver the result of a virtual screening campaign for drug discovery with the highest speed along with the highest accuracy. The full automation of the solution and the possibility to run it on multiple supercomputing centers at once permit to run an extreme scale in silico drug discovery campaign in few days to respond promptly for example to a worldwide pandemic crisis., Part of ISBN 9798400701405QC 20230919

Coarse-Grained Reconfigurable Arrays (CGRAs) are a class of reconfigurable architectures that inherit the performance of Domain-specific accelerators and the reconfigurability aspects of Field-Programmable Gate Arrays (FPGAs). Historically, CGRAs have been successfully used to accelerate embedded applications and are now considered to accelerate High-Performance Computing (HPC) applications in future supercomputers. However, embedded systems and supercomputers are two vastly different domains with different applications and constraints, and it is today not fully understood what CGRA design decisions adequately cater to the HPC market. One such unknown design decision is regarding the interconnect that facilitates intra-CGRA communication. Our findings show that even the typical king-style mesh-like topology is often under-utilized with a typical HPC workload, leading to inefficiency. This research aims to explore the provisioning of intra-CGRA interconnect for HPC-oriented workloads and, ultimately, recoup the potential performance and efficiency lost by reducing the interconnect complexity. We proposed several reduced interconnect topologies based on the usage statistic. Then we evaluate the tradeoffs regarding hardware cost, routability of DFGs, and computational throughput., Part of ISBN 9798350311990QC 20230919

Convolution has been widely employed in image processing and computer vision applications such as picture augmentation, smoothing, and structure extraction. In addition, convolution operations are the most prevalent computing patterns in machine learning domains. Convolutions, for example, are used in a substantial chunk of state-of-the-art convolutional neural network operations. Therefore, effectively mapping convolution operations onto hardware architectures is crucial for achieving superior performance while accelerating convolutional neural networks. In this paper, we proposed various algorithms to efficiently map the 2-D convolution operation onto a dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we have discussed the mapping of 2-D convolution on the target architecture for an input matrix of arbitrary size, as well as the generalization of the proposed approaches for multi-column DRRA architectures., Part of ISBN 9798400700439QC 20230919

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore's law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture- architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2Logic. Q2Logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on Field-Programmable Gate Arrays (FPGAs), but specialized towards quantum simulations. We described how Q2Logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2Logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2Logic can be up-to 7x faster., Part of ISBN 9798350311990QC 20230919

CRYSTALS-Kyber has been selected by the NIST as a public-key encryption and key encapsulation mechanism to be standardized. It is also included in the NSA's suite of cryptographic algorithms recommended for national security systems. This makes it important to evaluate the resistance of CRYSTALS-Kyber's implementations to side-channel attacks. The unprotected and first-order masked software implementations have been already analysed. In this paper, we present deep learning-based message recovery attacks on the omega-order masked implementations of CRYSTALS-Kyber in ARM Cortex-M4 CPU for omega <= 5. The main contribution is a new neural network training method called recursive learning. In the attack on an omega-order masked implementation, we start training from an artificially constructed neural network M-omega whose weights are partly copied from a model M omega-1 trained on the (omega - 1)-order masked implementation, and then extended to one more share. Such a method allows us to train neural networks that can recover a message bit with the probability above 99% from high-order masked implementations., QC 20230824

In embedded systems development, contract based design is a design paradigm where a system is divided hierarchically into components and developed in a top-down manner, using contracts as a means to divide responsibilities and manage the complexity of the system. Contract theories provide a formal basis for reasoning about the properties of the system, and of the contracts themselves. In previous work, we have developed a contract theory for sequential, procedural programs, that is defined abstractly, at the semantic level. The theory fulfils well-established, desired properties of system design. In this paper, we present a methodology for applying the contract theory in real embedded software design. We show how to instantiate the contract theory with concrete syntaxes for defining components and contracts, and how the contract theory enables formal reasoning about the resulting objects. In order to cope with the need for different behavioural models at different levels of abstraction in an embedded system, we extend the contract theory through parametrisation on the semantic domain. We illustrate the application of the proposed methodology on a small, but realistic example, where the temporal logic TLA is used for reasoning at the system level, while lower level components are specified using pre- and post-conditions in the form of ACSL, a specification language for C., Part of ISBN 9783031352560QC 20230821

With the advent of massively distributed applications such as those required by the IoT-to-Edge-to-Cloud compute continuum (i.e., automotive, smart agriculture, smart manufacturing, and more), real-time communication mechanisms allowing physically distributed nodes to seamlessly communicate as if they were running on the same host acquired noteworthy importance. To this end, the synchronous inter-process communication (IPC) mechanism provided by the QNX operating system (OS) is a promising candidate, as it allows using the application programming interface for communicating both on a single- and multi-node setting. Furthermore, it provides priority and partition inheritance mechanisms to improve predictability when working with the Adaptive Partitioning Scheduler (APS), a reservation-based scheduler provided by the QNX OS. This paper explores the behavior of the QNX synchronous message-passing (SyncMP) IPC with an extensive set of experiments, using them to formalize its behavior and model it from a real-time perspective. Then, it provides a response-time analysis for client-server applications based on the QNX SyncMP building upon self-suspending task theory. Finally, we evaluate the analysis on an application based on the WATERS 2019 Challenge by Bosch., QC 20230803

Fast-Fourier Transform is an important algorithm which is used in digital signal processing and communication applications. Furthermore, mixed-radix FFT provides flexibility and increases the speed of FFT computation. For real-time processing, efficient hardware implementation using reconfigurable architectures is preferred which can offer higher performance and flexibility. In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also providing the flexibility to select the radix for each stage of the FFT. The twiddle factor generator proposed in this architecture minimizes the memory requirements and simplifies the hardware. Using the proposed architecture, various length FFTs were mapped onto either single cell or multiple cells in parallel. It is observed that the proposed architecture improves the performance by 2x times when compared to the existing FFT architectures., QC 20230621

Photodetectors that convert light into electrical signals have become an indispensable element for a large number of technologies to enable extensive applications, ranging from optical communications to advanced imaging and motion detection, to automotive industry particularly including self-driving cars, and to astronomy and space exploration under harsh environment. The present photodetector market is predominated by silicon (CMOS-based) photodetectors. With the continuous growth of application areas, highly desired are photodetectors of higher performance in terms of speed, efficiency, detectable wavelength range, and integrability with semiconductor technology. These necessitate the development of new photodetectors based on special materials, rather than the conventional silicon single crystals, as building blocks for various advanced photodetection platforms. To this end, we summarize in this chapter the recent status of advanced photodetectors based on the emerging material, graphene. Our discussion includes the performance metrics, working mechanisms, practical implementation, as well as opportunities and challenges, for graphene-based photodetectors., QC 20230614

Side-channel attacks impose a serious threat to cryptographic algorithms, including widely employed ones, such as AES and RSA. These attacks take advantage of the algorithm implementation in hardware or software to extract secret information via side channels. Software masking is a mitigation approach against power side-channel attacks aiming at hiding the secret-revealing dependencies from the power footprint of a vulnerable implementation. However, this type of software mitigation often depends on general-purpose compilers, which do not preserve non-functional properties. Moreover, microarchitectural features, such as the memory bus and register reuse, may also leak secret information. These abstractions are not visible at the high-level implementation of the program. Instead, they are decided at compile time. To remedy these problems, security engineers often sacrifice code efficiency by turning off compiler optimization and/or performing local, post-compilation trans-formations. This paper proposes Secure by Construction Code Generation (SecCG), a constraint-based compiler approach that generates optimized yet protected against power side channels code. SecCG controls the quality of the mitigated program by efficiently searching the best possible low-level implementation according to a processor cost model. In our experiments with twelve masked cryptographic functions up to 100 lines of code on Mips32 and ARM Thumb, SecCG speeds up the generated code from 77% to 6.6 times compared to non-optimized secure code with an overhead of up to 13% compared to non-secure optimized code at the expense of a high compilation cost. For security and compiler researchers, this paper proposes a formal model to generate power side channel free low-level code. For software engineers, SecCG provides a practical approach to optimize performance critical and vulnerable cryptographic implementations that preserve security properties against power side channels., QC 20230522

All systems rely on inputs and outputs (I/Os) to perceive and interact with their surroundings. In safety-critical systems, it is important to guarantee both the performance and time-predictability of I/O operations. However, with the continued growth of architectural complexity in modern safety-critical systems, satisfying such real-time requirements has become increasingly challenging due to complex I/O transaction paths and extensive hardware contention. In this paper, we present a new NoC-based Predictable I/O system framework (NPRC-I/O) which reduces this contention and ensures the performance and timepredictability of I/O operations. Specifically, NPRC-I/O contains a programmable I/O command controller (NPRC-CC) and a runtime reconfigurable NoC (RNoC), which provides the capability to adjust I/O transaction paths at run-time. Using this flexibility, we construct an end-to-end transmission latency analysis and an optimisation engine that produces configurations for NPRCI/ O and the I/O traffic in a given system. The constructed analysis and optimisation engine guarantee the timing of all hard realtime traffic while reducing the deadline misses of soft real-time traffic and overall transmission latency.

A 3D bioprinter employing light-based technology has been designed and constructed in an EU-funded research initiative known as BRIGHTER (Bioprinting by Light-Sheet Lithography). This initiative is a collaborative effort between institutions and companies and aims to develop a technique for efficient and accurate production of engineered tissue. Presently, the bioprinter’s function is limited to 2D printing, with the lack of 3D printing capabilities. The problem addressed is the integration of two separate electronic systems within the bioprinter to control the laser beam’s trajectory for 3D printing. The goal of the project is to create functional software and simulation tools to control the hardware modules in a precise and synchronized manner, thereby enabling 3D printing. The outcome manifests as a software prototype, which successfully facilitates intercommunication between the two electronic subsystems within the bioprinter, thereby enabling further progress on the bioprinter with 3D printing available. Nevertheless, the prototype requires thorough testing to determine its optimal operational efficiency in terms of timing the movements for the various hardware modules., En 3D-bioprinter som använder ljusbaserad teknik har designats och konstruerats i ett EU-finansierat forskningsinitiativ som kallas BRIGHTER (Bioprinting by Light-Sheet Lithography). Detta initiativ är ett samarbete mellan institutioner och företag och syftar till att utveckla en teknik för effektiv och korrekt produktion av konstruerad vävnad. I dagsläget har bioprintern inte möjligheten för 3D-utskrift, utan är begränsad till 2D-utskrift. Problemet som åtgärdas är integrationen av två separata elektroniska system inom bioprintern för att styra laserstrålens bana för 3D-utskrift. Målet med projektet är att skapa funktionell mjukvara och simuleringsverktyg för att styra hårdvarumodulerna på ett exakt och synkroniserat sätt och därigenom möjliggöra 3D-utskrift. Resultatet av examensarbetet är en mjukvaruprototyp, som framgångsrikt möjliggör interkommunikation mellan de två elektroniska systemen inom bioprintern och därigenom öppnar möjligheten för vidare arbete med 3D-utskrift tillgängligt. Prototypen kräver dock noggranna tester för att fastställa dess optimala operativa effektivitet när det gäller koordinationen av hårdvarumodulernas rörelser.

This thesis explores the design and optimisation of a sensor system for real-time position determination of the Fish component in the CatFish naval drone and the development of a sonar sensor system for accurate object localisation and safe navigation in dynamic and uncertain underwater conditions. Through comprehensive experimentation and analysis, this thesis demonstrates the effectiveness of the proposed sensor system and sonar sensing system in enhancing underwater navigation and obstacle avoidance capabilities. Additionally, research will compare two sonar systems: one using more expensive MaxBotix sonar sensors that are plug-and-play and don't need a lot of extra interfacing and data analysis. The other system utilises the cheaper CUSA ultrasonic transducers which needs a surrounding circuit and extra data analysis to work. The findings help researchers select the right system and improve sonar technology by identifying limitations and proposing enhancements to the systems. The research offers insights into building a self-built beamforming sonar array and addresses the deficiencies of commonly used ultrasonic systems. It provides valuable guidance for engineers and contributes to the advancement of ultrasonic technologies. The study also offers a unique comparison between user-friendly systems and simple transducers, aiding engineers in choosing the appropriate system for their needs. Overall, it enriches the field's knowledge and guides future developments in sonar systems. This thesis contributes to the advancement of underwater navigation in autonomous naval vehicles, providing valuable insights and recommendations for the design and optimisation of sensor systems and sonar sensing systems. The findings have implications for improving the navigational capabilities of the CatFish drone and contribute to the scientific understanding of sonar system performance under diverse conditions., CatFish Project

Water is the source of all life, but unfortunately, the water quality is getting only worse due to many factors like overuse, contamination, indifference and even by nature itself. By identifying the problem, we are one step closer to solving the problem, and that is why an intelligent water quality device is required to examine water and detect impurities within it. In this project, we are developing a device that uses an entirely new method to measure water quality. Even though the theory behind the device is very advanced, the device is still primitive in its functions and needs development to increase the usefulness and accuracy of the measurements!, Vatten är grunden till allt liv, men tyvärr blir vattenkvaliteten bara sämre på grund av många faktorer som överanvändning, förorening, likgiltighet och till och med av naturen själv. Genom att identifiera problemet är vi ett steg närmare att lösa problemet, och detta är därför en intelligent vattenkvalitetsenhet behövs för att undersöka vattnet och hitta orenheter i det. I detta projekt utvecklar vi en apparat som använder en helt ny metod för att mäta vattenkvaliteten. Även om teorin bakom apparaten är väldigt avancerad så är apparaten fortfarande primitiv i sina funktioner och behöver utveckling för att öka användbarheten och noggrannheten i mätningarna!

This thesis report is about designing a prototype and establishing audio communication between a computer and Digital Signal Processor (DSP) using two preamp circuits using both auxiliary and USB connection. The paper gives the reader an overview on how audio is transmitted from a computer, through the system and to the desired output. The reader should also get a better understanding of how an AD-converter samples the incoming signal to the Discrete plane and how an AUX or phone connector works. This information can be used for designing preamp circuits to communicate between a computer and the DSP. The DSP circuit uses an STM32 processor to control the incoming and outgoing signals with the use of ADC and DAC conversion. The DSP also uses microphones to capture surrounding sound. An addition is to make a prototype on how to use these microphones to send the signal upstream to the computer. The microphone is then benchmarked with the use of Matlab, calculating Total Harmonic Distortion. Management and optimization of code structure and resources is done in the source files of the project. Using imperative C programing, large functions are broken down into smaller functions to ease readability and control flow. The result is a prototype circuit that can communicate audio signals with both audio jack and USB between computers input and output to the DSP. Using CubeMX in conjunction with CubeIDE to add additional ADC channels to be able to incorporate an automatic source control when the audio jack or USB is connected., Denna avhandling handlar om att designa en prototyp och etablera ljudkommunikation mellan en dator och en digital signalprocessor (DSP) med hjälp av två förstärkarkretsar genom både aux- och USB-anslutning. Rapporten ger läsaren en översikt över hur ljud skickas från en dator, genom systemet och till önskad utgång. Läsaren bör också få en bättre förståelse för hur en AD-omvandlare fungerar för att sampla den inkommande signalen till tidsdiskreta planet och hur en AUX- eller telekabel fungerar. Målet är att använda denna information för att skapa förstärkare som kan kommunicera mellan en dator och DSP:en. DSP-kretsen använder en STM32-processor för att hantera de inkommande och utgående signalerna med användning av ADC- och DAC-omvandling. DSP:en använder också mikrofoner för att fånga omgivande ljud. Ett tillägg är att skapa en prototyp för hur man kan använda en av mikrofonerna för att skicka signalen till datorn. Mikrofonen jämförs sedan med hjälp av Matlab genom att beräkna total harmonisk distorsion. Hantering och optimering av kodstruktur och resurser görs i projektets källkodsfiler. Genom att använda imperativ C-programmering bryts stora funktioner ned i mindre funktioner för att underlätta läsbarheten och styrningen av flödet. Resultatet är en prototypkrets som kan kommunicera ljudsignaler med både ljuduttag och USB mellan datorns in- och utgång och DSP:en. Genom att använda CubeMX tillsammans med CubeIDE läggs ytterligare ADC-kanaler för att möjliggöra automatisk källkontroll när ljuduttaget eller USB-anslutningen är ansluten.

Unmanned aerial vehicles (UAVs), commonly known as drones, have revolutionized numerous fields ranging from aerial photography to surveillance and logistics. Achieving stable flight is essential for their successful operation, ensuring accurate data acquisition, reliable manoeuvring, and safe operation. This thesis explores the feasibility of employing a frontal mono camera and sensor fusion techniques to enhance drone stability during flight. The objective of this research is to investigate whether a frontal mono camera, combined with sensor fusion algorithms, can be used to effectively stabilize a drone in various flight scenarios. By leveraging machine vision techniques and integrating data from onboard gyroscopes, the proposed approach aims to provide real-time feedback for controlling the drone. The methodology for this study involves the Crazyflie 2.1 drone platform equipped with a frontal camera and an Inertial Measurement Unit (IMU). The drone’s flight data, including position, orientation, and velocity, is continuously monitored and analyzed using Kalman Filter (KF). This algorithm processes the data from the camera and the IMU to estimate the drone’s state accurately. Based on these estimates, corrective commands are generated and sent to the drone’s control system to maintain stability. To evaluate the effectiveness of the proposed system, a series of flight tests are conducted under different environmental conditions and flight manoeuvres. Performance metrics such as drift, level of oscillations, and overall flight stability are analyzed and compared against baseline experiments with conventional stabilization methods. Additional simulated tests are carried out to study the effect of the communication delay. The expected outcomes of this research will contribute to the advancement of drone stability systems. If successful, the implementation of a frontal camera and sensor fusion can provide a cost-effective and lightweight solution for stabilizing drones

With the increasing need for low-cost, power-efficient computing units, RISC-Vas an open-standard Instruction Set Architecture (ISA) is becoming more and more popular in the industry. There are multiple open-source RISC-V soft processors like cva6, VEGA, NOEL-V and more. But those processors have a common problem in that they can only be implemented onto a specific FPGA development platform. This thesis introduces a new processor design with compatibility in mind so that it will not be limited to a certain development platform but can be used on multiple different platforms as far as they meet the basic requirements. This processor is a single-stage processor without any pipeline implemented. The processor is used to evaluate the power efficiency of the architecture and has a unique feature to enable or disable the RISC-V Compressed (RVC) instruction subset to understand its impact on power-efficient. It is simple in architecture but still has the full capability for the RV64IC instruction set. Because of it uses RISC-V architecture, in the future, this processor can be easily expanded to adopt more RISC-V instruction subsets.

Sprinting can be an important ability in sports, and there are many methods for measuring sprint performance. Two common methods are hand-held timing and fully automatic timing systems. However, hand-held timing is inaccurate due to reaction time, and fully automatic timing can be impractical since it involves complex equipment. Another way of measuring sprint performance is to obtain an athlete's velocity curve with a laser speed gun, although this requires that the laser is aimed towards the sprinter at all times. In this project, ultra-—widebandwhich is a radio technology capable of accurate —rangingis evaluated in a practical experiment by observing an athlete sprinting over a short distance. First, a pair of communicating ranging devices are developed. Measurements are then collected from the athlete and compared to video analysis to estimate the ranging error. The results suggest that ultra-wideband may be an alternative to laser speed guns for measuring sprint velocity. In the future, research should be focused on calibrating devices and testing ultra-wideband technology for longer sprint distances., Att kunna springa snabbt kan vara en viktig egenskap inom sport och det finns många metoder för att mäta en sprint. Några exempel är manuell tidtagning, automatiska tidtagningssystem eller laserpistol för att mäta hastighet. Ofta är manuell tidtagning inte tillräckligt noggrann på grund av reaktionstid och automatisk tidtagning kan vara opraktisk för de flesta utövare. Dessutom måste en laserpistol alltid vara riktad mot atleten för ge mätningar. I det här projektet testas ultrabredbandsteknik – vilket är en typ av radioteknik som kan ge noggrann distansmätning – i ett praktiskt experiment genom att observera en atlet i en kort sprint. Först utvecklas ett par apparater som kan avläsa distansen mellan varandra. Därefter samlas mätningar från atleten som jämförs med videoanalys för att bestämma mätningsfelet. Det erhållna resultatet föreslår att ultrabredbandsteknik kan vara ett alternativ till laserpistoler för hastighetsmätning inom sprint. Framöver borde fokus inom forskningen ligga på att kalibrera apparater och testa tekniken över längre sprintdistanser.

Introduction: This paper presented an analysis of the energy consumption and responsiveness of MicroPython in an embedded system. The purpose of this study was to understand the energy consumption and response time of a MicroPython based system to optimize its overall performance and efficiency. Two research questions had been formulated to concretize the purpose of this thesis: [RQ1] How does the energy consumption of a MicroPython based embedded system compare to that of a C-based embedded system for tasks utilizing low power modes? [RQ2] What is the wake-up response time of MicroPython for low power modes when receiving external and internal interrupts, and how does it compare to an established language like C on an embedded system? Method: To answer the research questions and achieve the purpose, an experimental study was conducted. The energy consumption of the MicroPython based system was analyzed under different scenarios. The time it took for MicroPython to respond to an interrupt request from a sleeping state was also measured. The data collected from the experiment was analyzed to determine the level of energy consumption and responsiveness of MicroPython in an embedded system. Results: The results indicated that C was generally more energy efficient and responsive than MicroPython for tasks utilizing low power modes for the Deepsleep mode. Although MicroPython proved to have shorter response times for the Lightsleep low power mode. For energy consumption, C was more stable in the measurements while MicroPython reached both lower minimum currents and higher maximum currents. Conclusions: In conclusion, this study found that while MicroPython could achieve lower power levels than C in both low power modes tested, it reached higher current levels upon waking up. Despite this, MicroPython could still be a choice for applications that spend longer durations in low power modes, as this could offset the increased current spikes during wake-up. Response times for