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Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm2, an input referred noise of 1.32 μVrms (1 to 200 Hz) and 3.36 μVrms (0.2 to 10 kHz), power consumption of 13.7 μW from 1.8 V supply, as well as CMRR and PSRR ≥ 83 dB at 50 Hz. [ABSTRACT FROM AUTHOR]

A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel reconfigurable transformer is proposed with more freedom to achieve a flexible load impedance tuning range of the sub-PAs. The characteristics of the reconfigurable transformer based on tunable inductors are analyzed. Efficiency enhancement is achieved at 3-/6-/9-/12-/15-dB PBOs without any supply switching or PA short-switches. The PA is fabricated in 40-nm CMOS technology with a core size of 0.83 mm2. Operating at 2.3–3.4 GHz, it introduces 24.2-dBm peak Pout with 38.5% peak drain efficiency (DE) at 2.8 GHz. It achieves 38.5%/29.6%/18.4% at 2.8 GHz and 34.7%/26.6%/17.8% DE at 3.3 GHz for 0-/6-/12-dB PBO, 39.3%/29.5%/14.9% at 2.8 GHz, and 35.3%/27.9%/15.9% DE at 3.3 GHz for 3-/9-/15-dB PBO, respectively. For 10-MHz 256-QAM modulation signal, it delivers 16.22-/15.50-dBm average Pout with EVM of −32.3/−33.0 dB, average DE of 24.6%/22.7%, and ACLR of −33.20/−31.54 dBc at 2.8/3.3 GHz, respectively. For 20-MHz 64 QAM modulation signal, it exhibits 16.42-/15.52-dBm average Pout with EVM of −29.1/−29.3 dB, average DE of 24.9%/22.78%, and ACLR of −30.78/−30.74 dBc at 2.8/3.3 GHz, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an active electromagnetic interference (EMI) choke for both common-mode (CM) and differential-mode (DM) noise suppression is proposed. Three isolated windings with a different number of turns are wound on the same magnetic core. One of the windings is served as the auxiliary winding connecting to an active circuit called the negative impedance circuit. The inductance of the EMI choke is substantially boosted up to effectively attenuate the low-frequency noise. This technique leads to a greater inductance but fewer turns and smaller size of the EMI choke. Different from the design of a conventional EMI filter, which uses separated CM and DM chokes, this proposal saves the cost and space of the EMI filter. The enhancement to the CM and DM impedance is individually analyzed and experimentally confirmed. Based on the classical CM and DM noise models, CM and DM noise insertion losses are predicted using computer simulation. The simulation results are validated by a network impedance analyzer. Finally, conducted EMI tests are carried out to verify the effectiveness of the proposed technique. [ABSTRACT FROM PUBLISHER]