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A short-circuit detection (SCD) circuit is proposed for power electronics systems that use silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( MOSFET s). The proposed SCD circuit incorporates a digital circuit for processing the voltage induced at the parasitic inductance of the source of SiC MOSFET to obtain an improved stable turn- off operation of the SiC MOSFET under SC condition. Compared with that of the conventional analog signal processing based SCD circuits, the proposed circuit has the advantages of having a turn- off operation which is robust to process, voltage, and temperature variations, being fully integrated without the use of external components and ease of design. The proposed circuit was implemented in a 350-nm Bipolar-CMOS-DMOS process. For functional verification, an SC test board integrating the proposed SCD circuit was developed. Experimental result validates that the proposed SCD circuit effectively functions under SC condition.

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves −35.8 dBm in-band input-referred third-order intercept point (IIP3), > −22.3 dBm out-of-band IIP3, and an average 3rd LO HRR of 43 dB over 300–800 MHz in DBM&HR mode. Over 600–1200 MHz in SHM mode, it shows >31.8 dB conversion gain, −30.9 dBm in-band IIP3, and > −20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.

This paper presents a highly efficient InGaP/GaAs HBT power amplifier (PA) implemented using a proposed high- $Q$ single- and two-winding transformer. A single- and two-winding transformer is designed with a printed circuit board (PCB) to combine the output power with a reduced passive loss. Compared to a typical 1:2 two-winding transformer, an additional unit amplifier is connected at the mid-point of the secondary winding to construct a single-winding transformer without additional windings. An IMD3 cancellation technique using a single- and two-winding transformer is also proposed to obtain a high linear output power with high power-added efficiency (PAE) without additional design circuitry. The IMD3 components of the two input currents in the single- and two-winding transformer are 180° out-of-phase cancelling each other at output. The proposed PA is integrated with an InGaP/GaAs HBT process using a PCB transformer. The experimental results demonstrate that the PA achieves a saturated output power of 33.3 dBm, with a PAE of 61.3% at 0.91 GHz. The proposed PA is also tested with an orthogonal frequency-division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signal having a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB at 0.91 GHz to evaluate the improvement in linearity. The PA achieves an adjacent channel leakage ratio (ACLR) of −42 dBc up to an output power of 26.0 dBm with a PAE of 26.8% and current consumption of 297 mA.

Design equations for the parameters of a lumped-element quadrature coupler with impedance transforming are derived. Considering on-chip implementations, it has a smaller size as compared to a quarter-wavelength transmission-line-based coupler. A 2.47-GHz quadrature coupler with impedance transforming is implemented using GaAs technology for verification. The measurement results show that the fabricated coupler achieves an insertion loss of 3.39 dB with a phase imbalance of 0.8° for through and coupled outputs at 2.47 GHz.

A dual mode InGaP/GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) using a parallel power-combining transformer (PCT) is presented herein. A low loss transformer is implemented on a printed circuit board (PCB) to improve the passive efficiency of a PCT. Dual-mode operation is applied to reduce the current consumption at a low power level. In the low-power (LP) mode, one of the individual amplifiers is turned off to reduce the current consumption. Additionally, a third-order intermodulation distortion (IMD3) cancellation method using a PCT combiner is proposed to improve linearity performance. Nonlinear IMD3 components from each amplifier cancel each other out through magnetic coupling in the secondary winding of the PCT. The implemented PA achieves a saturated output power of 33.8 dBm and a peak power-added efficiency (PAE) of 54.5% at 0.91 GHz with a 5-V power supply. An average output power of 25.2 dBm with an adjacent channel leakage ratio (ACLR) of −42 dBc is delivered when the PA is tested with an orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulated (64-QAM) signal with a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB. When compared with the high-power (HP) mode operation, the LP mode operation could save 48% of the current consumption at an average output power of 10.4 dBm.

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1–19.2/18.6–18.8 dBm in the respective ranges of 2.4–2.5/4.9–5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors’ knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9–5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far.

A 24-GHz direct-conversion transmitter is proposed for in-cabin radar applications. The proposed RF transmitter consists of an I/Q up-conversion mixer, an I/Q local (LO) oscillator generator, and a power amplifier. To improve the linearity of the I/Q up-conversion mixer, an inverter transconductor with third-order intermodulation (IM3) distortion cancellation is proposed. To improve the I/Q balancing performance of the I/Q LO generator, a poly-phase filter, including parasitic line inductance, is proposed. By employing a highly linear I/Q up-conversion mixer and a balanced I/Q LO generator, the 24-GHz direct-conversion transmitter achieves high linearity and I/Q balancing characteristics. It is fabricated in a 65-nm CMOS process and consumes 150 mW. It shows an OP1dB of 8.6 dBm, an LO leakage of &minus, 48 dBc, and an image rejection ratio of &minus, 49 dBc for the entire operating band from 24 GHz to 24.5 GHz.

This paper presents a linear CMOS power amplifier (PA) for mm-wave 5G applications. A compact 8-way parallel-parallel power combiner is proposed to increase Pout with low loss and symmetrical phase/amplitude. The IMD3 cancellation method is presented in this work to obtain a high linear P OUT with high PAE. The PA in 65-nm CMOS shows a 23.2dBm P OUT with 33.5% PAE for CW signals at 28GHz. It achieves the highest linear PAE of 17.6% at an average P OUT of 18.02dBm with -31.2dB EVM and -30dBc ACPR supporting a 256-QAM 100MSym/s signal at 28GHz.

A 24-GHz RF sensing receiver front-end with improved I/Q balanced LO generator is presented for a surveillance radar system. The proposed RF receiver front-end consists of a low-noise amplifier, an I/Q down-conversion mixer, and an I/Q local oscillator (LO) generator circuit. The proposed design method of a polyphase filter at millimeter-wave frequencies provides improved and balanced I/Q signals in comparison to a conventional polyphase filter. The receiver front-end draws 20-mA current from a 1.2-V supply voltage. The measured return loss of the RF input port is less than -10 dB in the range of 23.9–24.3 GHz. The receiver front-end achieves a conversion gain of 26.8 dB, noise figure (NF) of 5.1 dB, and an input 1-dB compression point (input P1dB) of -19.7 dBm in the 23.9–24.3 GHz range. Gain and phase mismatch between the I- and Q-paths at IF output are less than 0.15 dB and 0.3°, respectively.

An electronic warfare (EW) simulator is presented to investigate and evaluate the tracking performance of radar system under the electronic attack situations. The EW simulator has the input section in which the characteristic parameters of radar threat, radar warning receiver, jammer, electromagnetic wave propagation, and simulation scenario can be set up. During the process of simulation, the simulator displays the situations of simulation such as the received signal and its spectrum, radar scope, and angle tracking scope and also calculates the transient and root-mean-squared tracking errors of the range and angle tracking system of radar. Using the proposed EW simulator, we analyze the effect of concealment according to the noise and signal powers under the noise jamming and also analyze the effect of deception by calculating errors between the desired value and the estimated one under the deceptive jamming. Furthermore, the proposed EW simulator can be used to figure out the feature of radar threats based on the information collected from the EW receiver and also used to carry out the electronic attacks efficiently in electronic warfare.

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

A modified series combining transformer incorporating an autotransformer for the dual-mode operation to improve efficiency performance in the low-output power region is presented. The dual-mode CMOS power amplifier (PA) with the proposed reconfigurable transformer is fabricated using 40-nm CMOS technology. Compared with other dual-mode WLAN CMOS PAs, the proposed PA achieves high-efficiency performance in both high-power and low-power modes; in dual-mode operation, the PA has average output power levels of 19.2 and 15.2 dBm with power added efficiencies of 17.3 and 14.4%, respectively, while satisfying the error vector magnitude requirements of WLAN 802.11g signals.

This paper presents a UHF band (470–868 MHz) receiver front-end circuit that can support GSM interoperability(IOP) when a GSM receiver and a digital TV tuner receiver such as DVB-H coexist. The proposed receiver front-end circuit consists of a low-noise amplifier(LNA), a single-to-differential amplifier, and a current-mirror based I/Q downconversion mixer. A resistive feedback topology was used to receive wideband signals, and a LNA was constructed including notch filters to support GSM IOP. The proposed receiver frontend was designed using a 130nm RF CMOS process and consumes power of 14mW at supply voltage of 1.2V. The proposed receiver front-end shows a gain of 28dB, an IIP3 of −11 dBm, and a NF of 3dB at 470–748 MHz when the notch filter is operating, and a gain of 30dB, an IIP3 of −11dB, and a NF of 3dB at 470–868 MHz when the notch filter is not operational.