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With continually growing adoption of FPGA based designs, and more features and capabilities available in FPGAs, board and system level test applications can - and should - take advantage of FPGA embedded instrumentation. Such FPGA assisted tests not only improve manufacturing test but also allow extensive testing in the field to address issues such as no-fault-found syndrome by enabling the detection of environment-induced defects or latent defects (related to bad solder joint quality, aging, etc.). In this paper we are briefly reviewing different types of FPGA embedded instruments before specifically addressing synthetic instrumentation and focusing on example use cases. We will be discussing design for test considerations, quality of test and diagnostics, savings in test time and test cost, and levels of automation previously not associated with functional and performance / stress test development.

In this paper, we demonstrate a clear gap in board level test coverage under category of timing related faults (TRFs). Although there are techniques that are capable to detect TRFs, there is no fault coverage metrics to quantify the quality of these techniques. To do that, we propose an easy-to-implement interconnect-level fault model extension towards TRFs. This extension can be integrated into existing test coverage models providing additional information on coverage of timing-related faults.

This paper presents a method for optimization of board-level scan-test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra HW cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant overall test time reduction in comparison with traditional Boundary Scan approach.

A method is proposed for simulating of transition delay faults (TDF) at different fault propagation conditions. The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions like non-robust and functional sensitization. A new sensitization type, called nonrobust functional sensitization was introduced as well. A novel delay fault reasoning algorithm based on sequential 7-valued algebra is presented, which is used for fault coverage calculation separately for all mentioned four types of TDFs. By experimental results we established that the fault coverage share for different types of TDFs considerably depends on the quality of delay test.

This paper studies a new approach for board-level test based on synthesizable embedded instruments implementted on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration of system components thus minimizing the usage of external test equipment. By replacing traditional test and measurement equipment with embedded synthetic instruments it is possible not only to achieve the significant reduction of test costs but also facilitate high-speed and at-speed testing. We detail the motivation and classify the FPGA-based instrumentation into different categories based on the implementation and application domains. Experimental results show the efficiency of this approach.

The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2).

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. The authors will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated sequences. The authors will make the main focus on one optimization technique that is applicable to reseeding-based test generators and that uses a test compaction methodology. The technique exploits a great similarity in the way the faults are covered by pseudorandom sequences and by patterns generated for sequential designs. Hence, the test compaction methodology previously developed for the latter problem can be successfully reused in embedded testing.

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.

LFSR reseeding techniques are often applied in BIST due to their ability to considerably improve the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. The efficiency of a typical reseeding scheme to a large extent depends on the seed selection and consequent test sequence optimization algorithms. This paper proposes a novel efficient reseeding optimization algorithm that is based on test compaction techniques for sequential designs. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal test set compaction solution for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published reseeding and hybrid BIST results.

This paper describes a new software tool for high quality training/learning in the field of digital microelectronics. Its main purpose is to give insight into reliability and quality assurance technologies based on linear feedback shift registers (LFSR) and other pseudo-random pattern generators (PRPG). Various PRPG types are becoming the mainstream test generation solution used in built-in self-test (BIST) structures. Taking into account complex theoretical concepts behind the microelectronics self-testing (including data coding and compression, cryptography, field theory, linear programming) it is important to effectively educate engineers in this field. The software tool we present in this paper is aimed at facilitating this goal. Unlike other similar systems, this tool facilitates study of various test optimization problems, allows fault coverage analysis for different circuits and with different LFSR parameters. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The multi-platform JAVA runtime environment allows for easy usage of the tool both in the classroom and at home. The BIST Analyzer represents an integrated simulation, training, and research environment that supports both analytic and synthetic way of learning. Due to the above mentioned facts the tool provides a unique training platform to use in courses on electronic testing and design for testability.

Linear feedback shift registers (LFSR) and other pseudo-random pattern generators (PRPG) have become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers, and high-performance integrated circuits. The current paper describes a training and research tool for learning basic and advanced issues related to PRPG-based test pattern generation. Unlike other similar systems, this tool facilitates study of various test optimization problems, allows fault coverage analysis for different circuits and with different LFSR parameters. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The multi-platform JAVA runtime environment allows for easy access and usage of the tool both in a classroom and at home. The BIST analyzer represents an integrated simulation, training, and research environment that supports both analytic and synthetic way of learning. Due to the above mentioned facts the tool provides a unique training platform to use in courses on electronic testing and design for testability. The BIST Analyzer has got a positive feedback from students of Darmstadt TU (Germany) and Tallinn TU (Estonia).

Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization.

High-performance communication interfaces in modern complex electronic systems bring new challenges for board-level manufacturing test. Various means of calibration and error-correction that are incorporated into high-speed protocols tend to hide manufacturing flaws thus making comprehensive testing be an extremely hard task. Links transmitting at gigabit rates are especially susceptible to so-called marginal defects. Marginal defect often escape detection by commonly used test methods as they manifest themselves only under certain conditions that may sporadically occur during device operation in the field. As a result, undetected marginal defects badly affect system stability and reduce its overall operating margin. In this paper, we present a novel embedded instrumentation toolbox intended for use in volume production environments to screen out outliers and marginal devices. The paper focuses on instruments for testing marginal defects on High-Speed Serial Links and DDR3/4 interfaces.

The last decade has seen increasingly rapid growth in the prevalence of FPGA devices. Today, FPGAs are extensively used in all commercial sectors, like communications, consumer, military and industry. Test engineers also recognized a great potential of FPGAs for test and measurement (T&M) purposes. The main benefit of FPGA devices is a possibility for hardware reconfiguration. This feature turns FPGAs into a flexible hardware base for T&M instrumentation. Multiple different instruments can be implemented and executed on the same FPGA device, thus significantly reducing the expense of purchasing stand-alone hardware instruments. At the same time, FPGAs being integrated to the system can also be exploited as a platform for embedded instrumentation (EI) [1]. In this work, we consider an approach that temporarily reuses an existing on-board FPGA resource to carry out necessary manufacturing tests. As the allocated FPGA logic is reclaimed for functional use after the test is finished, the presented technique does not require hardware changes and thus does not introduce additional costs.