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Detailed state-space modeling and analysis of a class of RF switched-capacitor power amplifiers achieving high efficiency, output power, and linearity are presented. Time-domain voltage and current waveforms are analytically obtained via the steady-state solution of the amplifier’s model equations. The output power of the fundamental and that of the harmonics, as well as the drain efficiency of the switched-capacitor power amplifier (SCPA) are derived. The state-space model is implemented in MATLAB and all theoretical results are compared to Cadence Spectre simulation of the SCPA and are found to be in good agreement.

An optimization methodology for a popular class of differential RF switched-capacitor power amplifiers exhibiting high efficiency, output power and linearity is presented. Analytical maximization of the output power with respect to component values provides explicit formulas and design guidelines for the amplifier’s core and the tuning of the matching network, that can be used as a starting point for the design and trimming of the power amplifier circuit in an IC design environment.

The IEEE 802.11ad standard supports PHY rates up to 6.7Gb/s on four 2GHz-wide channels from 57 to 64GHz. A 60GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a full-featured 802.11ad chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset includes MAC, PHY, and RF with a PCIeTM interface and is capable of maintaining a link of 4.6Gb/s (PHY rate) at 10m.

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

To support increased device functionality and higher data-rates in LTE-enabled systems, while improving user experience and usage time, there is a need to reduce RFIC size and power consumption without degrading performance, while maintaining backward compatibility with legacy 2G/3G systems [1]. This paper introduces a 13mm2, 40nm CMOS 2G/HSPA+/TDSCDMA/UE cat. 4 transceiver that consumes 36/65mA battery-referenced current in 3G/LTE20 modes (B1, −50dBm TX, −60dBm RX). This is achieved in part by employing a multiport single-core LNA with a multitap inductor and a current-mode-driven single-core transmit mixer. Baseband-assisted calibration techniques help achieve 60dBm IIP2 in all bands. To save on platform area and cost, the RFIC supports single-ended LNAs, 32kHz clock generation, and free-running XTAL operation. TX SAW filters are not required.

Digital video reception is emerging as the latest feature toward multimedia-enriched handheld devices. Mobile battery-operated devices require small-size tuners that consume low power and are amenable to single-chip integration with the baseband demodulator. Following an overview of the system and circuit-level implementation challenges of mobile TV standards such as DVB-H and T-DMB, this article presents a dual-band direct conversion tuner for DVB-H. Architecture and circuit trade-offs are discussed, and detailed measurements are presented. The tuner occupies 9.7 mm2 and achieves a 4 dB NF at both UHF and L-band, eliminating the need for an external LNA. By using a fractional-TV synthesizer both 470-890 MHz and 1.4-1.8 GHz bands are supported, while achieving an integrated phase noise of less than -41 dBc. Sixth-order low-pass filters support channel bandwidths from 4 to 10 MHz

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.

State-space modeling and analysis of a class of switched capacitor RF power amplifiers are introduced resulting in fast and accurate calculation of the output and supply-drawn power as well as of the voltage and current waveforms. Power derivation parameterized on component values and intermediate transformed impedances offers a tool for optimizing the switched capacitor RF power amplifier for maximum output power or maximum Power Added Efficiency. The accuracy of the derived results is verified with SPECTRE (Cadence) simulation.

A direct conversion, 65 nm CMOS multi-standard TV tuner is presented, which is compliant with several digital terrestrial, fixed and mobile TV standards (DVB-T, DVB-H, T-DMB and ISDB-T, including 1-3 segment). The tuner achieves a 3/3/2.8 dB NF at VHF, UHF and L-band respectively, while consuming less than 140 mW in DVB-T mode. By using integrated transformers, both single-ended and differential RF inputs are supported. Multi-standard capability is enabled by programmable channel-select filters and a Sigma-Delta fractional-N synthesizer.

A zero-IF, 4.9-5.95 GHz, 2.3-2.5 GHz, transceiver is fabricated on a 0.18 /spl mu/m CMOS process. By using a fractional-N synthesizer, an integrated phase error of 0.6/spl deg/ (0.7/spl deg/) at 5 GHz (2.4 GHz) is achieved, while supporting fine frequency resolution. Digital calibration eliminates I/Q mismatch and achieves accurately matched baseband filters. The transceiver is compliant to 802.11a/b/g, while programmable bandwidth filters and an EVM of -35 dB in both transmit and receive, make it suitable for applications based on 802.16d/e.

A 0.18mum CMOS direct-conversion dual-band DVB-H receiver occupies 9.7mm2 and achieves a 4dB/5dB NF at UHF/L-band, eliminating the need for an external LNA. By using a fractional-N synthesizer, the 470 to 890MHz and 1.4 to 1.8GHz bands are supported while achieving an integrated phase noise of

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 /spl mu/m CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on both TX/RX paths, thus minimizing area. It features a NF of 3.5 dB while the sensitivity is -78 dBm at 54 Mb/s operation, referred at the input of the chip. The transmit output 1 dB compression point is 9 dBm. Digital calibration helps achieve an EVM of -31 dB while transmitting -4 dBm at 54 Mb/s.

A dual band, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, zero-IF transceiver is fabricated on a 0.18/spl mu/m CMOS process. The fully integrated synthesizer and VCO achieve an integrated phase error of 0.8/spl deg/ at 5GHz. The transmitter achieves -33dB EVM, while the receiver features a 5.2dB noise figure (NF) at 5.25GHz and 3.5dB NF at 2.45GHz. An architecture including feedback paths enables digital calibration, which help eliminate I/Q mismatch and achieve accurately matched baseband filter tuning.

This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for transmit/receive and a PLL synthesizer frequency range of 4.9 to 5.85GHz with -79dBc/Hz phase noise at 10kHz offset have been measured. The IC is realized in 0.5/spl mu/m SiGe BICMOS technology and occupies 17mm/sup 2/.

In this paper a new behavioral modeling approach for RF systems based is presented, based on a Volterra series input-output map representation. The modeling is done purely in the frequency domain, capturing the typical system level specifications for RF building blocks, independent of the implementation details. A harmonic balance simulation tool has been developed based on those models. The implementation focuses on deterministic effects such as distortion and frequency conversion. The behavioral simulator has been tested for various systems and results are presented.