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We present analytical models for calculating surface potential for both undoped (intrinsic) and doped (extrinsic) long channel symmetric double-gate MOSFETs. Starting with Poisson’s equation, we derive the implicit surface potential equation(s) for the symmetric double-gate MOSFET in the accumulation and depletion/inversion regions of operation. This results in a continuous surface potential curve throughout all operating regions of the device. By introducing a defect potential to surface potential equations for the symmetric double-gate MOSFET, the models add the effects of oxide-trapped charge and interface traps (both uniform and non-uniform distributions) that can build up in the gate dielectric of the device. A drain current model is presented for both the undoped and doped cases of the SDG MOSFET. The accuracy of the surface potential analytical models and drain current models are validated by comparing to numerical results from two dimensional TCAD simulations.

This chapter opens with a discussion of the author’s personal thoughts and experiences post-launch in Games User Research. Its subsequent sections explore data sources that should be leveraged on a live title, and the importance and limitations of benchmark studies. The chapter concludes with a methodological example that can be implemented to kick-start your own post-launch analysis.

In this work we are first to report an explicit solution to the SPE for a dynamically-depleted DD-SOI MOSFET that captures the effects of both oxide-trapped charge and interface traps on the device characteristics. Derivations for both the implicit (iterative) and explicit (non-iterative) solutions to the surface potential equation are presented for the DD-SOI MOSFET device. The explicit or closed form approximation was solved using non-iterative techniques that have been developed for the PSP MOSFET compact modeling framework (Wu, 2007; Chen and Gildenblat, 2001, 2005). The non-iterative model can be implemented as a Verilog-A sub-circuit module using a VCVS in series with the gate of the SOI MOSFET that is compatible with standard circuit level simulation tools. We demonstrate the accuracy of the implicit and explicit surface potential-based derivations using two dimensional TCAD simulations as a comparison. Finally, we present the symmetric linearization method for computing the drain current of the DD-SOI MOSFET.

This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling.