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DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We equip real web-based Chromebook computers with the Intel Optane solid-state drive (SSD), which contains state-of-the-art low-latency NVM, and use the NVM as swap space. We analyze the performance and energy consumption of the Optane-equipped Chromebooks, and compare this with (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-the-art NAND-flash-based SSD. Our experimental analysis reveals that while Optane-based swap space provides a cost-effective way to alleviate the DRAM capacity bottleneck in consumer devices, naive integration of the Optane SSD leads to several system-level overheads, mostly related to (1) the Linux block I/O layer, which can negatively impact overall performance; and (2) the off-chip traffic to the swap space, which can negatively impact energy consumption. To reduce the Linux block I/O layer overheads, we tailor several system-level mechanisms (i.e., the I/O scheduler and the I/O request completion mechanism) to the currently-running application’s access pattern. To reduce the off-chip traffic overhead, we leverage an operating system feature (called Zswap) that allocates some DRAM space to be used as a compressed in-DRAM cache for data swapped between DRAM and the Intel Optane SSD, significantly reducing energy consumption caused by the off-chip traffic to the swap space. We conclude that emerging NVMs are a cost-effective solution to alleviate the DRAM capacity bottleneck in consumer devices, which can be further enhanced by tailoring system-level mechanisms to better leverage the characteristics of our workloads and the NVM.

In this paper, we propose a practical disk error recovery scheme tolerating multiple simultaneous disk failures in a typical RAID system, resulting in improvement in availability and reliability. The scheme is composed of the encoding and the decoding processes. The encoding process is defined by making one horizontal parity and a number of vertical parities. The decoding process is defined by a data recovering method for multiple disk failures including the parity disks. The proposed error recovery scheme is proven to correctly recover the original data for multiple simultaneous disk failures regardless of the positions of the failed disks. The proposed error recovery scheme only uses exclusive OR operations and simple arithmetic operations, which can be easily implemented on current RAID systems without hardware changes. [Copyright &y& Elsevier]

We describe a simulation environment that allows us to simulate the standard peripheral component interconnect (PCI) bus protocol, as well as modified PCI protocols. While there are standard benchmarks (such as the SPEC [IEEE Comput. 33 (7) (2000) 28] benchmarks) available for processor simulation, database system simulation, and now even for simulating embedded systems (from EDN Embedded Microprocessor Benchmarking Consortium, EEMBC, http://www.eembc.org), there are no standard benchmarks for simulating computer buses in general and specifically, for simulating the PCI bus. To address this problem we describe a methodology for gathering information about the PCI traffic from a real system, and to use this information in order to generate PCI cycles that drive the simulator for both standard and modified PCI protocols. Finally, we use the simulation environment to run experiments with various parameters of the standard PCI protocols, and an extension that involves transferring a hint about the expected latency on the data bus at the time the target ends the current burst transaction. [Copyright &y& Elsevier]

The transaction ordering problem of the original PCI 2.1 standard bus specification violates the desired correctness property of maintaining the so called ‘Producer/Consumer’ relationship between writers and readers of data. This violation stems mainly from the so called completion stealing problem, first identified and solved by Corella et al. [4], and supported by a formal paper and pencil argument. In this paper, we develop a flexible graph theory library in PVS for modeling computer bus structures, formalize the PCI 2.1 protocol containing the solution of [4] in it, and mechanically prove the absence of completion stealing. Next, we define the Producer/Consumer property in PVS and sketch its mechanical proof. Noting the complexity of this proof effort (unfinished as yet), we explore a combination of theorem proving and model-checking in which the model used for model-checking is made tractable by exploiting the formal theorems established during theorem-proving as well as several intuitively justified assumptions. The theorem-proving infrastructure we have built for modeling CPU interconnect structures is highly reusable. Our work is one example of a natural division of labor between theorem-proving and model-checking in tackling system-level verification problems under realistic time budgets. [ABSTRACT FROM AUTHOR]

Previous studies on disk scheduling for video services were usually based on computer simulation. We present analysis on disk scheduling for video services. This paper first gives a short review on the various disk scheduling algorithms. It then concentrates on the analysis of two major disk scheduling algorithms, namely, CLOOK and LOOK. The purpose of the analysis is to obtain the maximum number of simultaneous users supported by systems using these two algorithms. The results of the analysis show that the CLOOK algorithm performs slightly better than LOOK algorithm in video applications. Then, this paper discusses disk scheduling for supporting special user functions such as “forward search” and “reverse search”. It is shown that the maximum number of user streams supported drops dramatically when such user functions are used. A technique called redundancy for special user functions (RESUF) is then studied. Analysis of the technique shows that it can keep the I/O demands to almost constant under all user request conditions [ABSTRACT FROM PUBLISHER]

A driver is the part of an I/O system used for processing of an I/O request for a specific channel. The interaction of the CPU with a channel is described through the monitor concept of Hone and Brinch Hansen. The implementation of monitors using hardware interrupt facilities is described. The resulting device monitor is compared with the device processes of Wirth's Modula. The concept is illustrated through an extension to Concurrent Pascal with examples drawn from the PDP11 system. Problems of missing interrupts and power failure are also discussed. [ABSTRACT FROM AUTHOR]

The discrepancy between the capacities of mass storage devices and main memory of computing systems is here to stay. The article introduces the concept of cost effective filtering with various options such as basic filter for selections, concurrent filtering extension for selections and projections, and concurrent filtering extension incorporating dynamic filtering for join, projection, and selection. After presenting these, detailed performance modeling of the filtering options is provided. Based on these performance models, a simulator is constructed and experiments for comparative filtering performance assessments are conducted. The results showed performance gains on the part of the systems employing filtering, especially in environments where high selectivities and concurrency are involved. [ABSTRACT FROM AUTHOR]