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This article presents a full-duplex (FD) rake receiver (RX) that uses the orthogonality properties of pseudo-noise (PN) codes to reject transmitter (TX) self-interference (SI) in the RF domain, allowing simultaneous transmit and receive (STAR) operation in the same frequency channel. The rake RX also exploits multipath propagation in wireless channels and PN code orthogonality to gather signals across multipath components to increase the signal-to-noise ratio (SNR) while avoiding the fading effects of multipath channels. The rake RX shares a low-noise amplifier (LNA) between the three rake fingers and a high-linearity baseband (BB) section with the second-order filtering to improve the rejection with low power consumption. Measurements indicate that TX SI rejection is 41.2 dB in the RF domain with 9-dB SNR improvement in a multipath channel. The rake RX is implemented in a 45-nm RFSOI CMOS process and occupies an active area of 1.6 mm2 while consuming 45.8 mW per finger, including clock power consumption.

This article presents a CMOS-based, code-domain (CD), full-duplex (FD) transceiver operating in a link at 1 GHz. The CD FD link rejects in-band transmitter self-interference (TX SI) by more than 100 dB through a combination of pseudo-noise (PN) code orthogonality, circulator, and digital cancellation algorithms. A nonmagnetic CMOS circulator based on switched transmission lines is used as an antenna interface with >40-dB maximum rejection. Then, transmitter (TX) and receiver (RX) modulators spread the TX SI and correlate the desired RX signal in the RF domain. Orthogonality between the PN codes allows an additional >40-dB maximum rejection relaxing the FD transceiver linearity requirements. Finally, digital self-interference cancellation (SIC) eliminates any residual TX SI in the digital domain using a least mean squares (LMS) estimation for the SI channel based on a nonlinear truncated Volterra series model. The digital SIC can have almost 40 dB of rejection depending on the SI power level. An implemented FD node leverages these techniques to achieve an overall rejection that is around 104 dB bringing the TX signal from 20 dBm to the noise floor of the RX at −85 dBm.

Code-domain signal processing techniques implemented at radio frequencies (RFs) enable simultaneous transmit and receive (STAR) applications. With direct sequence spread spectrum (DSSS) techniques and RF correlators, transmit (TX) self-interference (SI) is separated from the receive (RX) signal at the antenna interface for STAR. The processing gain inherent in the code-domain approach increases the TX SI rejection in the RF domain to relax filtering and linearity requirements of the RX. A code-domain RX demonstrates 52 dB of TX SI rejection with TX code-notch and RX code-pass filters operating at the same center frequency. The RX is tunable from 0.25 to 1.25 GHz and has a gain of 39 dB at 1 GHz while consuming 90 mW of which 40 mW are consumed in the front-end filters. The RX is implemented in a 45-nm CMOS SOI process and full-duplex operation is verified through an over-the-air demonstration.

This article demonstrates a signal processing technique for receiving non-contiguous RF channels by concurrently mixing several RF bands to adjacent IF channels. Consequently, channel selection does not require local oscillator tuning and the proposed receiver (RX) can switch channels in less than 25 ns. The RX chip operates over a frequency range of 100 MHz–1.4 GHz and demonstrates an out-of-band rejection of 49 dB and a measured RX sensitivity of −86 dBm, which is the lowest measured for $N$ -path-based RXs. The chip was fabricated in a 45-nm RF silicon-on-insulator (SOI) CMOS process and occupies an active area of 0.55 mm2 with the power consumption of 23.1 mW when operating at 1 GHz. The chip performance is verified with over-the-air measurement of two transmitted signals 80 MHz apart that are received simultaneously with a 10-MHz analog-to-digital converter (ADC) at an error vector magnitude (EVM) around −20 dB. The measured dynamic range for EVM less than −20 dB is better than 86 dB for a QPSK constellation.

This letter presents a tunable notch filter that can be reconfigured to improve rejection while offering high power handling. The notch filter uses a series $N$ -path filter in conjunction with an impedance-transformed shunt $N$ -path filter to improve the transmit (TX) rejection or notch concurrent bands. A 4th-order notch provides >40-dB rejection for a single TX channel. In the dual-notch mode, the notches can be tuned to two different TX channels. Finally, a low-power single-notch mode provides >20-dB rejection with low power consumption. The filter is implemented in a 45-nm CMOS SOI process and consumes between 11.9 and 43.9 mW at 1-V supply across a tuning range from 0.45 to 0.9 GHz while providing a peak rejection >50 dB and $P_{1~{\mathrm{ dB}}}$ as high as 15.8 dBm.

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch.

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ( $\lambda /4$ ) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes.

This paper presents a 3-finger rake receiver (RX) that exploits multipath characteristics in PN-modulated received signals to improve the signal-to-noise ratio (SNR) in full-duplex (FD) links. Orthogonality between PN codes allows up to 41.2 dB of TX self-interference (TX-SI) rejection and autocorrelation between delayed versions of received PN code improves the SNR by 9 dB. The receiver is implemented in 45-nm SOI CMOS and is tunable from 0.4 to 1.4 GHz with 30.5 dB of gain and an in-band/out-of-band baseband IIP3 of -6.5/14.2 dBm while consuming 45.8 mW per finger.

This paper describes a full-duplex (FD) radio transceiver that uses CMOS RFICs to realize high power handling and linearity. A high-rejection, magnetic-less CMOS circulator at the antenna along with high-rejection, blocker-tolerant RF code-domain correlators achieve high transmitter (TX) rejection in the RF domain. Code-domain operation supports higher linearity in FD applications. Digital cancellation increases the rejection down to noise floor of a software-defined radio (SDR). We compare the role of antenna impedance in the performance of SI rejection. The measured results demonstrate more than 104 dB TX self-interference (TX-SI) rejection at 20 dBm TX power. To the best of our knowledge, this work presents the best reported TX-SI rejection at more than 20 dBm.

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance.

A series code selective filter (CSF) for full-duplex communication is presented. The CSF passes a desired signal in a frequency band only when the signal is tagged with a pseudonoise (PN) code that matches the code at the filter. This approach is shown to reject a transmit signal in the same band as a desired receive signal. The coded transmitter signal is orthogonal through appropriate code selection from a codebook and the PN sequence spreads the signal energy outside the filter bandwidth (BW). The CSF achieves a self-interference rejection of 23.2 dB over a 10-MHz BW using on-chip generated Walsh codes. The CSF operates from 300 to 675 MHz and consumes 28.2 mA from a 1-V supply at 500 MHz. The CSF achieves an IIP3 of 15.7 dBm. The CSF was implemented in a 45-nm CMOS silicon on insulator process and occupies an area of 0.9 mm2.

This paper demonstrates a code-domain transceiver that incorporates a transmit (TX) modulator and receive (RX) RF signal correlator. We propose a transmission gate switch with 12.1-dBm/23.1-dBm P1dB/IIP3 for both RF correlation and filtering and rejects TX self-interference by 49.5 dB. An integrate-and-dump N-path filter improves rejection by 8 dB. The RX power consumption is 18 mW at 1 GHz. The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Megachip-per-second (Mc/s). Over the air testing demonstrates synchronization with Barker codes.

This work reports a high-power modulator implemented in 45-nm CMOS SOI for signal processing after the power amplifier. Two stacked switch variations, a 12 stack and 8 stack, were designed in 45-nm SOI CMOS and tested for trade-offs in insertion loss and power handling. These switches use a novel tapering technique to significantly improve switch linearity. The modulators have P 1dB values between 34 dBm and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1 GHz carrier. The IIP3 is between 46 dBm and 61 dBm.

This paper presents a code-domain receiver (RX) for simultaneous transmit and receive (STAR) applications. The RX achieves 52 dB of transmitter self-interference (TX SI) rejection through the application of direct sequence spread spectrum (DSSS) techniques at the antenna. The rejection is achieved through a cascade of code notch (CN) and code pass (CP) filters operating at the same center frequency. The integrated RX is tunable from 0.25 GHz to 1.25 GHz with 39 dB of gain at 1 GHz. The RX is implemented in a 45-nm CMOS SOI process and occupies an area of 2.6 mm2 including the filters, a low noise amplifier (LNA), and baseband circuits.

This paper reports a Watt-level power handling modulator using a stacked-FET switch for signal processing at the antenna. Two design approaches are compared in this paper: a resistive gate termination and an inductive gate termination. The stacked switches are implemented in 45-nm CMOS SOI. Measured performance of these stacked switches shows the benefit of an inductive termination: power handling capabilities of $> 30\ \mathbf{dBm}$ with modulation speeds of up to 300 MHz. The IIP3 is demonstrated to exceed 45 dBm.