Search

To meet commercialization requirements, the distributions of materials in hafnium-based ferroelectric devices—including their phase and orientation—need to be controlled. This article presents a method for improving the ferroelectric phase ratio and orientation by adjusting the stress distribution of the annealing structure in a three-dimensional capacitor. In such a structure, stress can be applied in three directions: tangential, axial, and radial; there are, thus, more ways to regulate stress in three-dimensional structures than in two-dimensional structures. This work sought to clarify the role of the stress direction on the proportions and orientations of ferroelectric phases. The results of stress simulations show that a structure with an internal TiN electrode, but no filling provides greater axial and tangential stresses in the hafnium-oxide layer. In comparison with the case of the hole being filled with tungsten, the proportion of the O phase is increased by approximately 20%, and in experiments, the projection of the polarization direction onto the normal was found to be increased by 5%. Axial and tangential stresses are regarded to be beneficial for the formation of the O phase and for improving the orientation of the polarization direction. This work provides a theoretical basis and guidance for the three-dimensional integration of hafnium-based ferroelectric materials. [ABSTRACT FROM AUTHOR]

We conducted a comprehensive investigation on the influence of TiN thickness and stress on the ferroelectric properties of Hf 0.5 Zr 0.5 O 2 thin films. TiN top electrode layers with varying thicknesses of 2, 5, 10, 30, 50, 75, and 100 nm were deposited and analyzed. It was observed that the in-plane tensile stress in TiN films increased with the thickness of the TiN top electrode. This is expected to elevate the tensile stress in the Hf 0.5 Zr 0.5 O 2 film, consequently leading to an enhancement in ferroelectric polarization. However, the effect of stress on the ferroelectric behavior of Hf 0.5 Zr 0.5 O 2 films exhibited distinct stages: improvement, saturation, and degradation. Our study presents novel findings revealing a saturation and degradation phenomenon of in-plane tensile stress on the ferroelectric properties of polycrystalline Hf 0.5 Zr 0.5 O 2 films, thereby partially resolving the discrepancies between experimental observations and theoretical predictions. The observed phase transformation induced by tensile stress in Hf 0.5 Zr 0.5 O 2 films played a crucial role in these effects. Furthermore, we found that the impact of the TiN top electrode thickness on other factors influencing ferroelectricity, such as grain size and oxygen vacancies, was negligible. These comprehensive results offer valuable insights into the influence of stress and TiN top electrode thickness on the ferroelectric behavior of Hf 0.5 Zr 0.5 O 2 films. [ABSTRACT FROM AUTHOR]

Hf0.5Zr0.5O2 (HZO) is a promising candidate for low-power non-volatile memory due to its nanoscale ferroelectricity and compatibility with silicon-based technologies. Stress and oxygen vacancy (VO) are key factors that impact the ferroelectricity of HZO. However, their combined effects have not been extensively studied. In this study, we investigated the impact of the VO content on HZO thin films' ferroelectricity under different electrode stresses by using TiN and tungsten (W) top electrodes and controlling ozone dose time during HZO deposition. The HZO thin films with W top electrodes exhibit elevated stress levels and a greater abundance of orthorhombic/tetragonal phases, and the HZO thin films with TiN top electrode shows an increase in the monoclinic phase with increasing ozone dose time. The residual polarization (Pr) of the capacitors with TiN and W top electrodes displayed different or even opposing trends with increasing ozone dose time, and the VO content decreases with increasing ozone dose time for both sets of capacitor samples. We propose a model to explain these observations, considering the combined influence of electrode stresses and VO on the free and formation energy of the crystalline phase. Increasing the VO content promotes the transformation of the tetragonal phase to the orthorhombic phase in HZO films with TiN top electrodes, and with W top electrodes, a higher VO content prevents the tetragonal phase from transforming into the orthorhombic/monoclinic phase. Additionally, an alternative explanation is proposed solely from the perspective of stress. These findings provide valuable insights into the regulation of ferroelectricity in HZO thin films. [ABSTRACT FROM AUTHOR]

HfO 2 -based thin films have raised considerable interest in ferroelectric memory devices due to their thickness scalability and process compatibility with CMOS. Stress exhibits a significant influence on ferroelectric polarization in HfO 2 -based films. However, the effect of stress has yet to be clarified despite numerous efforts, and there has been a lack of systematic review to collate and discuss this effect. This paper briefly introduces how stress is characterized in HfO 2 -based polycrystalline films as basis. Then, the process in which stress affects ferroelectricity is carefully discussed. The paper subsequently elaborates both the effects of out of plane stress and in plane stress. Furthermore, the interaction between stress and other factors is presented. Finally, the up-to-date research on the effect of stress are summarized, and several further research challenges for researchers are provided. Given the ubiquitous stress during the chip manufacturing process, a detailed summary of the stress effect has technological implications for processing and applications of HfO 2 -based thin films. [ABSTRACT FROM AUTHOR]

The ferroelectric field effect transistor (FeFET) is a very promising candidate for low-power and non-volatile memory. However, the co-existing effect of ferroelectric polarization and interface charge trapping in the FeFETs is demonstrated and many efforts have been made to eliminate this charge-trapping effect, which is usually treated as a deleterious effect. In contrast, we have found that the charge-trapping effect can play a dominant role in ferroelectric gates. In this work, we have verified that the charge-trapping effect of the ferroelectric/insulator interface could induce a memory window as the main physical mechanism in the TiN/Hf0.5Zr0.5O2/SiO2/p-Si (MFIS) structure, in which the ferroelectric characteristics of HZO thin films was verified through a reverse-grown MFIS structure. We also demonstrated that 2.5 nm SiO2 is optimal for the charge tunneling effect and the device has the largest memory window. Moreover, in order to enlarge the memory window of MFIS capacitors, we utilized the stress-enhanced ferroelectric polarization characteristics of Hf0.5Zr0.5O2 to improve the charge-trapping effect. Such a finding demonstrates that the ferroelectric-aided charge-trapping devices are potential to be used in non-volatile memories. [ABSTRACT FROM AUTHOR]

The 3-D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity (Arikan 2009). However, the 3-D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct a Polar Code in the NAND flash memory. This letter proposes a new Polar Code construction method called dynamic merge Monte Carlo (DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate (UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%. [ABSTRACT FROM AUTHOR]

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm 2 . The modulator occupies 1.41 mm 2 and the decimator occupies 0.55 mm 2 . [ABSTRACT FROM AUTHOR]