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This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16 nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95 K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.

In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-off in drain current due to intersubband scattering is experienced in the transfer characteristic with a certain V back . Moreover, resonant and source-to-drain tunneling transports are observed in devices with minimal channel length at cryogenic temperatures. The threshold voltage, V T , and free carrier mobility, µ eff , and their dependence on the back-gate voltage over a wide range of temperatures are extracted and discussed in detail. This work aims at investigating the impact of back gate potential on V T and carrier transport at cryogenic temperatures, further paving the way towards up-scaling of quantum computers.

This paper presents an in-depth DC characterization of a 22 nm FDSOI CMOS technology down to deep cryogenic temperature, i.e., 2.95 K. The impact of the back-gate voltage (V-back) on device performance, i.e., threshold voltage (V-T) and carrier transport, is investigated over a wide temperature range. Moreover, semiclassical and quantum transports of two-dimensional carrier gas are investigated. The effective mobility (mu(eff)) extracted from short devices at cryogenic temperatures is lower than actual mobility due to the presence of ballistic transport. The discontinuous I-D-V-G is found in both long and extremely short transistors, which is ascribed to the intersubband transition happening during the scattering event. Oscillatory I-D-V-G due to resonant tunneling manifests itself in short devices at cryogenic temperatures and depends on V-back. On the other hand, the worse subthreshold swing is found for short devices in the saturation regime and at cryogenic temperatures due to source-to-drain tunneling.

International audience; In this work, we present an experimental method that allows for a proper distinction between oxide (front or back) and semiconductor traps in FDSOI MOSFETs, using all four bias terminals. To this end, two cases of Random Telegraph Noise (RTN) measured signals are studied. It is shown that this method can also be used to localize the trap across the channel. Furthermore, the trap's electrostatic impact is proven to be misleading when it comes to trap localization in nanoscale devices.

In a MOSFET transistor, the subthreshold swing defines the switching efficiency, and the associated slope factor, or so-called body factor, is a critical parameter in charge-based models. However, in an advanced Fully -Depleted Silicon-On-Insulator (FDSOI) process, the slope factor is influenced by a strong back gate coupling due to a thin buried oxide (BOX). A conventional constant expression cannot describe the slope factor at various back-gate voltages. Therefore, this paper proposes a general slope factor expression for front-and back-gate transfer characteristics of long-channel FDSOI MOSFETs in a strong gate coupling. The proposed expression is a continuous function of the surface potential difference between the front and back sides, which explains the slope factor behavior versus the back-gate voltage. Besides, the systematic study is presented for the front/back interface states. The proposed model is applied to evaluate the down-scaling of FDSOI technologies in terms of the gate-coupled slope factor. The scaling in the buried oxide layer degrades the front slope factor, which a thinner channel or a reverse body bias can compensate for at the cost of a higher vertical electric field. Compared to the SiO2, the application of high -x dielectric for the buried oxide layer shows a better stand to the degraded slope factor by the interface states.

The work presents the comprehensive design-oriented EKV model for FDSOI technologies, including the backgate effects and geometry dependence. Despite its simplicity, the model correctly captures not only the dependence of the threshold voltage versus the back-gate voltage, but also the changes in the slope factor and low-field mobility. This results in a normalized transconductance efficiency that becomes independent of the back-gate voltage over a wide range. The model is validated thanks to the use of the Python-based automated parameter extraction tool on a 22nm FDSOI technology.