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A hundred watt level compact femtosecond laser system comprised of a high gain, low nonlinearity silicate glass fiber amplifier and a highly efficient Yb:YAG single-crystal fiber amplifier is demonstrated. By reducing the harmful thermal lens effect of amplifiers and optical elements, and precisely tuning dispersion of the stretcher, 110 W, 495 fs laser output at 1 MHz repetition rate and 250 μJ, 494 fs laser output at 200 kHz repetition rate are obtained. An optimized beam-quality factor (M 2) of better than 1.3 is obtained by filtering the beam with a small-aperture diaphragm. To our best knowledge, this is the first demonstration of such a hybrid femtosecond laser over 100 W and 100 μJ with good beam quality.

Ultrafast fiber lasers combining high peak power and excellent beam quality in the 1-µm wavelength range have been explored to applications in industry, medicine and fundamental science. Here, we report generation of a high-energy sub 300 fs polarization maintaining fiber chirped pulse amplification (CPA) system by using a Yb-doped large mode area tapered polarization maintaining (PM) optical fiber with the core/cladding diameters of 35/250 µm at the thin end and 56/400 µm at the thick end. The taper fiber design features a confined core for selective gain amplification and multi-layer cladding for enhanced suppression of higher order modes. In this regime, we have demonstrated 266 fs pulse amplification with peak power of up to 132 MW at a repetition rate of 2 MHz and high beam quality with measured M2 value of 1.1∼1.3. To the best of our knowledge, it is the highest peak power reported in such tapered Yb-doped fiber (T-YDF) amplifier in the femtosecond regime. This work indicates the great potential of the T-YDF to realize further power scaling, high laser efficiency, and excellent beam quality in high-power femtosecond fiber lasers.

Reverse transcription-quantitative polymerase chain reaction (RT-qPCR) is a molecular biological method used to assess gene expression characterized by high simplicity, effectiveness, specificity and sensitivity. The selection of a suitable reference gene for normalization is critical for the accuracy of quantitative results. Peripheral nerve injury is a common clinical disorder that affects multiple tissues and organs, including peripheral nerves, neurons and the innervated muscles. Numerous genes are differentially expressed in skeletal muscles during muscle denervation and reinnervation following peripheral nerve injury. The identification of a suitable reference gene in innervated muscles following nerve injury may improve the understanding of the alterations in gene expression in the processes of peripheral nerve repair and regeneration. Therefore, in the present study, by using a rat sciatic nerve crush model, the expression levels of various housekeeping genes were examined. In particular, the expression levels of 13 housekeeping genes, including 18S ribosomal RNA, actin β, ankyrin repeat domain 27, cyclophilin A, GAPDH, hypoxanthine phosphoribosyltransferase 1 (HPRT1), mitochondrial ribosomal protein L10, phosphoglycerate kinase 1, RPTOR independent companion of mammalian target of rapamycin complex 2, TATA-box binding protein, ubiquitin C, UBX domain protein 11 and tyrosine 3-monooxygenase/tryptophan 5-monooxygenase activation protein ζ, were investigated in gastrocnemius muscles. The geNorm and NormFinder analyses suggested that the expression level of HPRT1 was particularly stable in gastrocnemius muscles following rat sciatic nerve crush injury. Therefore, HPRT1 may be used as a reference gene for the normalization of gene expression data generated by RT-qPCR.

In this letter, a multiple-input–multiple-output (MIMO) antenna for 5G base stations is manufactured utilizing three-dimensional (3-D) printing technology. A high-resolution printer based on 3-D stereo lithography is induced to ensure the printing accuracy. The printing process of the proposed antenna with a size of 27.2 × 27.2 × 17 mm3 can be completed within half an hour. The printed sample is made of a kind of photosensitive resin, so all of its surfaces are metalized as the conductive surfaces of the antenna using a metal plating method. The characteristics of the 3-D printed antenna are investigated. The bandwidth of the antenna is measured to be 3.5–5.1 GHz. The antenna is composed of two orthogonal polarized dipoles. In the bandwidth, both the voltage standing-wave ratios of the two dipoles are below 1.5, and the isolation between the two dipoles is better than 18 dB. The far-field radiation patterns of the antenna in both the horizontal and vertical planes are measured in an anechoic chamber. All the characteristics of the proposed antenna are also simulated using High Frequency Structure Simulator. The measured and simulated results are in good accordance.

As the widely studied next-generation memory, spin-torque transfer random access memory (STT-MRAM) has a tendency to replace the traditional memory architecture. In this paper, the feasibility of integrating STT-MRAM into resources constrained IoT application is researched. Then a System-on-Chip (SoC) architecture based on STT-MRAM for smart card chip is proposed. Prototype verification results on a DE2 FPGA platform demonstrate that the STT-MRAM based SoC architecture can greatly improve the performance of both the ECC and AES coprocessor. According to the synthesis result in SMIC 40nm CMOS technology, the equivalent gate area of the STT-MRAM based SoC is 88K and the average power consumption is 3.284mW. All of those characteristics make the realization of STT-MRAM based SoC architecture for smart card chip promising.

Achyranthes bidentata polypeptides (ABPP), an active polypeptides isolated from the aqueous extract of Achyranthes bidentata Blume, contributes to the regeneration of injured peripheral nerves by promoting migration of Schwann cells (SCs). In this study, we aimed to investigate the possible mechanism underlying the ABPP-induced migration of primary cultured rat SCs. Transwell migration assays indicated that ABPP promoted SCs migration in a concentration-dependent manner by inducing production of NADPH-oxidase (NOX)-derived reactive oxygen species (ROS). Inhibition of ROS production by NOXs inhibitor apocynin (APO) or diphenyleneiodonium (DPI) partially blocked ABPP-mediated SCs migration. Furthermore, by using real-time polymerase chain reaction analysis and siRNA interference technique, we verified the participation of NOX subunit 4 (NOX4) and dual oxidase 2 (DUOX2) in ABPP-induced ROS production and consequential SCs migration. Taken together, these results demonstrated that ABPP promoted SCs migration via NOX4/DUOX2-activated ROS in SCs.

Pharmacological treatment is a therapeutic approach to improving nerve regeneration and functional recovery after peripheral nerve crush injury. The objective of the present study was to investigate the effects of the polypeptides isolated from Achyranthes bidentata Blume (abbreviated as ABPP) on rat sciatic crush injury and to test the possible involvement of neurotrophic factors. After surgical crush injury, rats received daily intraperitoneal injection of 0.2 ml saline containing 2 mg ABPP, 1 μg nerve growth factor (NGF) or no additive. The results from walking track analysis, electrophysiological assessment and histological evaluation indicated that the repair outcomes by ABPP treatment were close to those by NGF treatment, but better than those by treatment with saline alone. The quantitative real-time RT-PCR was used to monitor the mRNA expression of growth associated protein in the crush nerves and the mRNA expression of NGF, brain-derived neurotrophic factor (BDNF), ciliary neurotrophic factor (CNTF), tyrosine kinase (Trk)A and TrkB in the dorsal root ganglia (DRGs) at L4-L6. The mRNA expression of these genes in the crush nerve sample and DRGs sample was higher after treatment with ABPP or NGF than after treatment with saline alone. Our findings suggest that ABPP might protect peripheral nerve against crush injury through stimulating release of neurotrophic factors and the other cytokines.

An efficient algorithm is presented to label the connected components in the case that the primary memory is smaller than the image data. Our algorithm uses only the memory of two image rows to label the huge image or any image larger than the available memory. The search path compression is a applied for improving the performance further. An extensive comparison with the state-of-art algorithms is proposed, both on random and real datasets. Our algorithm shows an impressive speedup, while the auxiliary memory is not required at all comparing with all competitors.

A novel line-based streaming labeling algorithm with its VLSI architecture is proposed in this paper. Line-based neighborhood examination scheme is used for efficient local connected components extraction. A novel reversed rooted tree hook-up strategy, which is very suitable for hardware implementation, is applied on the mergence stage of equivalent connected components. The reversed rooted tree hook-up strategy significant reduces the requirement of on-chip memory, which makes the chip area smaller. Clock domains crossing FIFOs are also applied for connecting the label core and external memory interface, which makes the label engine working in a higher frequency and raises the throughput of the label engine. Several performance tests have been performed for our proposed hardware implementation. The processing bandwidth of our hardware architecture can reach the I/O transfer boundary according to the external interface clock in all the real image tests. Beside the advantage of reducing the processing time, our hardware implementation can support the image size as large as 4096*4096, which will be very appealing in remote sensing or any other high-resolution image applications. The implementation of proposed architecture is synthesized with SMIC 180nm standard cell library. The work frequency of the label engine reaches 200MHz.

A novel labeling algorithm is proposed in this paper for high-resolution image connected components labeling. The proposed method successfully solves the labeling problem in the case that the computer memory capacity is less than required for the existing algorithms. Unlike the conventional algorithms that have to load the entire image into memory for labeling, our algorithm can finish the labeling task with the memory requirement of only two image rows size. Comparison and tests for high-resolution images are performed with the state-of-the-art algorithm. The proposed algorithm achieves significant performance improvement for high-resolution images labeling.

A fast and efficient algorithm is presented to label the connected components for binary image, especially for very huge images or any image larger than the available memory. The cascading style scheme compresses the algorithm's workspace to only 2 rows of image, which makes it possible to process any scale image with very low memory requirement. Two techniques are also applied for improving the performance further: the search path compression; the image data prefetching. An extensive comparison with the state-of-art algorithms is proposed, both on random and real datasets. Our algorithm shows an impressive speedup as much as 10X, while the total memory cost is significantly reduced.

This paper presents a fast connected component labeling algorithm based on line description method and optimized tree Union-Find strategy. The algorithm transforms the pixel-connected issue, which most of proposed algorithms focus on, into line-connected issue. This algorithm is comprised of three phrases, line extraction, connected component identification and label assignment. The line description method transforms the connected pixels into line form for reducing the scan time. While the new tree Union-Find strategy diminishes the redundant root compare operations. A comparison analysis is performed with other optimized famous component labeling algorithms. Our algorithm has shown an outstanding performance with respect to the processing time, which achieves 1.1~8 times as fast as the other algorithms in various test cases.

As the demand of higher image quality and greater processing capabilities are growing, obtaining higher data bandwidth for on-chip processing is becoming a more and more important issue. DMA (Direct Memory Access) component, as the key element in stream processing SoC (System on Chip) [1], should be deeply researched and designed to satisfy the high data bandwidth requirement of processing units. In this paper, we introduce a scalable high-performance DMA architecture for complex SoC to satisfy rigorous high sustained bandwidth and versatile functionality requirements. Several techniques and structures are proposed in this paper. An integrated verification environment is also built for our design to fully verify its functionality. And the performance improvement by using our architecture is analyzed. At the end of the paper, the post-simulation and tape-out results are provided. The whole implementation has been silicon proven to be functional and efficient.

With the development of uncertain theory, fuzzy multi attribute decision making has been applicated in more and more areas. Sometimes, attribute value and attribute weight are given in the form of fuzzy numbers. This paper researches the fuzzy multi attribute decision making in which the fuzzy numbers are given in the form of interval numbers, first, the concept of interval numbers are given, then positive ideal point and negative ideal point of interval numbers are defined. This paper gives the distance between interval numbers, through computing the distance between each alternative and positive, negative ideal point of interval numbers, finds out each alternative’s closeness degree for ideal point, this paper gives a new method for fuzzy multiple attribute decision making, orders the alternatives according to closeness degree. Finally, this method is applicated in investment project chosen for new product development, through the example, the method’s validity and feasibility are verified.

With the development of uncertain theory, fuzzy multi attribute decision method has been applicated in more and more areas, this paper applies fuzzy multi attribute decision method in the assessment of investing enterprise. In modern society, social economy has developed rapidly, the investor has more and more opportunities to invest. Because of the complexity and uncertainty of objective things and the fuzziness of manpsilas thinking, the investment always has certain risk, if the evaluation about investment target is inaccurate, which will cause blindness in investment, then the investment profit canpsilat take back, so the assessment method on investing enterprise is very important. Information entropy is a kind of quantity of the system uncertainty, this paper researches the method of fuzzy multi attribute decision method based on information entropy, uses information entropy to decide attribute weight, and applies it in the assessment of investing enterprise, the example shows that this method is effective.

Two of the most significant factors in the success of todaypsilas system-on-chip (SoC) designs are the ability to deliver efficient access to off-chip high speed memory and the ability to be compatible with several different interface-timings of several different sorts of memories. And the scheduling scheme of data streams for multi-master and multi-outstanding requests situation in complex SoC should be considered carefully, too. This paper introduces a novel general external memory interface (GEMI) architecture for the high performance and high flexibility memory interface. Several techniques and methods, i.e. data and command buffers based on asynchronous FIFO, optimized bank management, multi-port access scheduler, request reorder unit, are proposed in this paper for fulfilling the requirements mentioned above. Some techniques are specially proposed for data streams scheduling in complex SoC. At the end of the paper, the simulation and tape-out results are provided. The whole implementation of architecture is proven to be not only functional and efficient, but also flexible and reusable by simulation and silicon verification.

An efficient two-scan connected component labelling (CCL) algorithm is proposed for a general purpose graphics processing unit (GPGPU). Compared to other GPU CCL algorithm, this algorithm has three distinct features. First, block-based and run-based strategies are combined in the first scan to simplify the equivalence label resolving process. Secondly, a novel labelling method for the GPU is introduced by constructing a forest of rooted trees using only 16-bit value for each node. Thirdly, the whole algorithm can be implemented in the GPU shared memory and minimise global memory bandwidth consumption. Experiments show that the algorithm achieves a speedup of between two and five times compared to other state-of-the-art GPU and CPU CCL algorithms.

A fast stripe-based connected component labelling algorithm is proposed for binary image labelling. Stripe extraction strategy is used to transform the pixel-connected issues, which most of the previously proposed algorithms focused on, into stripe-connected issues. The stripe-union strategy treats the combination of the neighbouring stripes as the mergence of rooted trees. Finally, comparisons are performed with other famous fast labelling algorithms. The proposed algorithm has shown better performance than the state-of-the-art algorithm in real images test, while the auxiliary memory is not required at all compared with all competitors.