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We experimentally demonstrate back-end-of-the-line (BEOL) compatible ( ${I}_{D{,SAT}}$ of $370~\mu \text{A}/\mu \text{m}$ , and on–off ratio $> 4\times 10^{9}$ at ${V}_{DS} = 1$ V and ${V}_{GS}$ – ${V}_{TH}= 2$ V. We identify fundamental transport mechanisms that limit electron mobility in amorphous IWO transistors at different gate-bias ( ${V}_{GS}$ ) and temperature. Benchmarking reveals that amorphous IWO FETs are promising candidate for in situ transistor fabrication in the BEOL for enabling high-performance monolithic 3-D (M3-D) integrated circuits.

The electronic transport properties of amorphous In$_{2} \mathrm{O}_{3}(\mathrm{a} - In _{2} \mathrm{O}_{3})$ are investigated from first principles simulations for BEOL transistor application. It is determined that local atomic and electronic structure disorders in a-In 2 O 3 are the fundamental origin of reduced mobility in amorphous phase. Medium range order In-In connectivity is responsible for the electron conduction pathway. It is found that amorphous disorder present in a-In 2 O 3 could induce shallow donor states and acceptor states that are responsible for the device threshold voltage instability. Nonstoichiometric defects including indium vacancy and interstitial will further increase the density of these defect states intrinsic to a-In 2 O 3 . The results could provide a better understanding of the electronic transport behavior in a-In 2 O 3 and useful insights for future defect controlling for better device performance.

The manufacturers of high-performance logic have been ardent champions of Moore's Law, which has resulted in exponential increase in aerial transistor density to 100 million transistors per square millimeter of silicon real estate. However, it is the memory chip makers who have taken the first step toward escaping the confines of scaling within the horizontal plane and have embraced the vertical or the third dimension. The dynamic random access memory manufacturers have adopted stacked capacitors that tower above the silicon plane that hosts the access and peripheral transistors, whereas the nand flash memory technologists can stack 128 layers of charge trap flash cells on top of each other in a monolithic fashion. To enable monolithic three-dimensional (M3D) integration of high-performance logic, one needs to solve the fundamental challenge of low temperature (

In this work, we evaluate the role of polarization switching and charge trapping in the operation of ferroelectric FET (FeFET) through combined experimental characterization and comprehensive modeling. We are demonstrating that: 1) the significant charge gap in the quasi-static split-CV (QSCV) and small signal CV is fundamental and not indicative of trapped charge density. This is because the QSCV senses the irreversible polarization switching while the small signal CV mainly probes the reversible domain wall displacement under ac excitation, theoretically yielding different scales of charge response in the two measurements. 2) Trapped charge density during memory write can be inferred from the measured charge release dynamics with the help of a comprehensive FeFET model that incorporates both the polarization switching and the charge trapping and release dynamics.

We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf 0.5 Zr 0.5 O 2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget ( 2 O 3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2P R , of 40μC/cm2 reliable with switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >108 cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3× higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.

We experimentally demonstrate BEOL compatible ( $\mathrm{I}_{\mathrm{D},\mathrm{SAT}}$ of $370\mu\mathrm{A}/\mu\mathrm{m}$ , and on-off ratio> 4×109 at $\mathrm{V}_{\mathrm{DS}} =1\mathrm{V}$ and $\mathrm{V}_{\mathrm{GS}}-\mathrm{V}_{\mathrm{T}}=2\mathrm{V}$ We provide insight into the electrostatic gate control efficiency through temperature and frequency dependent admittance measurement. We identify fundamental transport mechanisms that limit electron mobility inamorphous IWO as a function of gate-bias $(\mathrm{V}_{\mathrm{GS}})$ and temperature. Benchmarking shows that IWO DGFET is a promising BEOL transistor for enabling high-performance monolithic three-dimensional (M3D) integrated circuits.

We demonstrate a novel ferroelectric (FE) superlattice based multi-level cell (MLC) memory, which outperforms previous multi-state FE memory implemented using partial polarization switching, from the standpoint of device-to-device variation. We show that the FE superlattice consisting of alternate FE and dielectric (DE) thin layers provides a scalable approach for MLC implementation because: 1) the superlattice constructs controlled layer-by-layer polarization switching in the constituent FE layers; 2) the number of FE layers equals the number of stored bits; and, finally, (3) the switching of all the domains in a given coercive field (E C ) distribution associated with one isolated peak suppresses the variation induced by partial polarization switching. Based on these, we experimentally demonstrate a 2-bit/cell FE superlattice memory and simulate a 3-bit/cell memory with excellent device-to-device variation.

We demonstrate a novel strategy to scaling the equivalent oxide thickness (EOT) of MOSFETs by tuning the composition of Hf 1-x Zr x O 2 thin-film near morphotropic phase boundary (MPB) between orthorhombic ferroelectric phase and tetragonal anti-ferroelectric phase. This approach can avoid the shortcomings of mobility and reliability degradation incurred in interlayer (IL) scaling approach and gate leakage increase from band gap reduction in traditional higher κ materials. Through comprehensive theoretical modeling and experimental characterization, we show that: 1) MPB exists in Hf 1-x Zr x O 2 system due to phase transformation from orthorhombic phase to tetragonal phase with the increase of Zr concentration, in order to reduce the dipole-dipole interaction energy between the oxygen sub-lattices under compression; 2) κ is maximum (κ=38) near the MPB around 70% Zr as two phases co-exist and even a slight perturbation creates a large charge response; 3) Higher κ in advanced technology node FinFET improves the electrostatics and boosts drive current by 13%, suggesting that this strategy is a promising approach to designing high-κ dielectrics for the next generation CMOS.

Lyme disease is an infectious disease caused by the Borrelia burgdorferi bacterium. Early diagnosis of Lyme disease could prevent patients from developing serious side effects such as chronic arthritis and permanent neurological disorders. Lyme disease diagnosis is currently held back by a lack of reliable tools that are sufficiently sensitive and specific to allow early stage detection. Here, we demonstrate all electronic nano-biosensors for multiplexed detection of antigens of B. burgdorferi at concentrations as low as 2 pg ml−1. The sensors are based on graphene field-effect transistors (GFETs) coupled with genetically engineered antibody fragments. Single-chain variable fragment (scFv) antibodies are used to obtain a closer proximity of the target-binding event to the graphene sensor surface and for higher immobilization density. When compared to GFET nano-biosensors that use the parental immunoglobulin G (IgG) antibodies, scFv GFET nano-biosensors achieve approximately a 4000 × improvement to the limit of detection. We also demonstrate multiplexed detection of B. burgdorferi antigens through site-specific immobilization of scFvs on GFET arrays, which can potentially reduce the false-positive diagnosis ratio of Lyme disease. This work offers a pathway towards point-of-care detection of Lyme disease at an early stage.

Modern development of chemical manufacturing requires a substantial reduction in energy consumption and catalyst cost. Sunlight-driven chemical transformation by metal oxides holds great promise for this goal; however, it remains a grand challenge to efficiently couple solar energy into many catalytic reactions. Here we report that defect engineering on oxide catalyst can serve as a versatile approach to bridge light harvesting with surface reactions by ensuring species chemisorption. The chemisorption not only spatially enables the transfer of photoexcited electrons to reaction species, but also alters the form of active species to lower the photon energy requirement for reactions. In a proof of concept, oxygen molecules are activated into superoxide radicals on defect-rich tungsten oxide through visible-near-infrared illumination to trigger organic aerobic couplings of amines to corresponding imines. The excellent efficiency and durability for such a highly important process in chemical transformation can otherwise be virtually impossible to attain by counterpart materials.