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Structured growth of high quality graphene is necessary for technological development of carbon based electronics. Specifically, control of the bunching and placement of surface steps under epitaxial graphene on SiC is an important consideration for graphene device production. We demonstrate lithographically patterned evaporated amorphous carbon corrals as a method to pin SiC surface steps. Evaporated amorphous carbon is an ideal step-flow barrier on SiC due to its chemical compatibility with graphene growth and its structural stability at high temperatures, as well as its patternability. The amorphous carbon is deposited in vacuum on SiC prior to graphene growth. In the graphene furnace at temperatures above 1200$^\circ$C, mobile SiC steps accumulate at these amorphous carbon barriers, forming an aligned step free region for graphene growth at temperatures above 1330$^\circ$C. AFM imaging and Raman spectroscopy support the formation of quality step-free graphene sheets grown on SiC with the step morphology aligned to the carbon grid.

The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing., Comment: 15 pages, 7 figures

A method is proposed to extract pure Raman spectrum of epitaxial graphene on SiC by using a Non-negative Matrix Factorization. It overcomes problems of negative spectral intensity and poorly resolved spectra resulting from a simple subtraction of a SiC background from the experimental data. We also show that the method is similar to deconvolution, for spectra composed of multiple sub- micrometer areas, with the advantage that no prior information on the impulse response functions is needed. We have used this property to characterize the Raman laser beam. The method capability in efficient data smoothing is also demonstrated., Comment: 3 figures, regular paper

The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si-face epitaxial graphene used in the prior high frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high {\kappa} dielectric T-gate and self-aligned contacts, further contributed to the record-breaking fmax.

Graphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable graphene devices are essentially limited to micron size ultrahigh frequency analog field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges that severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high quality ribbons and rings can be made using this technique. We also report on progress towards high mobility graphene monolayers on silicon carbide for device applications., Comment: J. Phys D - Epitaxial Graphene special issue (submitted)

The thermoelectric response of high mobility single layer epitaxial graphene on silicon carbide substrates as a function of temperature and magnetic field have been investigated. For the temperature dependence of the thermopower, a strong deviation from the Mott relation has been observed even when the carrier density is high, which reflects the importance of the screening effect. In the quantum Hall regime, the amplitude of the thermopower peaks is lower than a quantum value predicted by theories, despite the high mobility of the sample. A systematic reduction of the amplitude with decreasing temperature suggests that the suppression of the thermopower is intrinsic to Dirac electrons in graphene., Comment: 5 pages, 4 figures

After the pioneering investigations into graphene-based electronics at Georgia Tech (GT), great strides have been made developing epitaxial graphene on silicon carbide (EG) as a new electronic material. EG has not only demonstrated its potential for large scale applications, it also has become an invaluable material for fundamental two-dimensional electron gas physics showing that only EG is on route to define future graphene science. It was long known that graphene mono and multilayers grow on SiC crystals at high temperatures in ultra-high vacuum. At these temperatures, silicon sublimes from the surface and the carbon rich surface layer transforms to graphene. However the quality of the graphene produced in ultrahigh vacuum is poor due to the high sublimation rates at relatively low temperatures. The GT team developed growth methods involving encapsulating the SiC crystals in graphite enclosures, thereby sequestering the evaporated silicon and bringing growth process closer to equilibrium. In this confinement controlled sublimation (CCS) process, very high quality graphene is grown on both polar faces of the SiC crystals. Since 2003, over 50 publications used CCS grown graphene, where it is known as the "furnace grown" graphene. Graphene multilayers grown on the carbon-terminated face of SiC, using the CCS method, were shown to consist of decoupled high mobility graphene layers. The CCS method is now applied on structured silicon carbide surfaces to produce high mobility nano-patterned graphene structures thereby demonstrating that EG is a viable contender for next-generation electronics. Here we present the CCS method and demonstrate several of epitaxial graphene's outstanding properties and applications.

Since its inception in 2001, the science and technology of epitaxial graphene on hexagonal silicon carbide has matured into a major international effort and is poised to become the first carbon electronics platform. A historical perspective is presented and the unique electronic properties of single and multilayered epitaxial graphenes on electronics grade silicon carbide are reviewed. Early results on transport and the field effect in Si-face grown graphene monolayers provided proof-of-principle demonstrations. Besides monolayer epitaxial graphene, attention is given to C-face grown multilayer graphene, which consists of electronically decoupled graphene sheets. Production, structure, and electronic structure are reviewed. The electronic properties, interrogated using a wide variety of surface, electrical and optical probes, are discussed. An overview is given of recent developments of several device prototypes including resistance standards based on epitaxial graphene quantum Hall devices and new ultrahigh frequency analog epitaxial graphene amplifiers., Comment: 18 pages, 10 figures to be published in J. Phys. D, special Issue on Carbon Related Materials Cluster

The quantum Hall effect, with a Berry's phase of $\pi$ is demonstrated here on a single graphene layer grown on the C-face of 4H silicon carbide. The mobility is $\sim$ 20,000 cm$^2$/V$\cdot$s at 4 K and ~15,000 cm$^2$/V$\cdot$s at 300 K despite contamination and substrate steps. This is comparable to the best exfoliated graphene flakes on SiO$_2$ and an order of magnitude larger than Si-face epitaxial graphene monolayers. These and other properties indicate that C-face epitaxial graphene is a viable platform for graphene-based electronics., Comment: Some modifications in the text and figures, 7 pages, 2 figures

The observation of the anomalous quantum Hall effect in exfoliated graphene flakes triggered an explosion of interest in graphene. It was however not observed in high quality epitaxial graphene multilayers grown on silicon carbide substrates. The quantum Hall effect is shown on epitaxial graphene monolayers that were deliberately grown over substrate steps and subjected to harsh processing procedures, demonstrating the robustness of the epitaxial graphene monolayers and the immunity of their transport properties to temperature, contamination and substrate imperfections. The mobility of the monolayer C-face sample is 19,000 cm^2/Vs. This is an important step towards the realization of epitaxial graphene based electronics., Comment: Two pages, 1 figure. Submitted to Science Brevia

Three types of first generation epitaxial graphene field effect transistors (FET) are presented and their relative merits are discussed. Graphene is epitaxially grown on both the carbon and silicon faces of hexagonal silicon carbide and patterned with electron beam lithography. The channels have a Hall bar geometry to facilitate magnetoresistance measurements. FETs patterned on the Si-face exhibit off-to-on channel resistance ratios that exceed 30. C-face FETs have lower off-to-on resistance ratios, but their mobilities (up to 5000 cm2/Vs) are much larger than that for Si-face transistors. Initial investigations into all-graphene side gate FET structures are promising.