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High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent work on design of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch correction algorithms in FPGA devices, over a broad band of input signal frequencies. Tests were also conducted to evaluate the systems performance, and the results indicate that the Effective Number of Bits (ENOB) is enhanced to be better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after correction, almost the same with that of the ADC chip employed.

This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area. The proposed technique gives the first order approximation of the gain mismatches and sample-time mismatches, and employs first order approximation FIR filter banks to calibrate the sampled signal, which do not need large number of FIR taps. In the case of a two-channel 12-bit TIADC, the proposed technique improves SINAD of simulated data from 45dB to 69dB, and improves SINAD of measured data from 47dB to 53dB, while the number of FIR taps is only 30. In the case of slight mismatches, 24-bit FIR coefficient is sufficient to correct 12-bit signals, which makes it easy to implement this technique in hardware. In addition, this technique is not limited by the number of sub-ADC channels and can be calculated in parallel in hardware, these features enable this technique to be versatile and capable of real-time calibration.

A 256-channel time-of-flight (TOF) electronics system has been developed for a beam line facility called "Back-n WNS" in China Spallation Neutron Source (CSNS). This paper shows the structure and performance of electronics system and the test results in CSNS. A 256-channel photomultiplier tube (PMT) is chosen as the detector in this system. In order to acquire the time information from the PMT, an electronics system has been designed. The electronics system mainly includes one front-end board (FEB), four time-to-digital converter (TDC) boards and one clock distribution module (CDM). There are 256 channels on FEB and 64 channels on each TDC board. The FEB is connected to the PMT with high-density connectors and the TDC boards are connected to the FEB through 2m cables. The TDC boards are 6U size so that they can be PCI extensions for Instrumentation (PXI) cards. Data from TDC boards can be transferred to the PXI control card through the backboard. In order to make four TDC boards work synchronously, a CDM outputs four clock signals to TDC boards which are distributed from one clock source. The TDC boards achieve a timing resolution of 3.5ns by test with a signal generator. The TOF measurement system has been used in CSNS.

To test and calibrate various detectors in nuclear and high energy physics experiments, a general purposed calibration instrument has been developed. All information including timing, amplitude and charge of signals can be directly obtained to calibrate detector with this instrument by amplifying and digitizing the signal waveform. The system consists of two parts, a large dynamic range pre-amplifier module and a high speed and high-resolution digitization module. The pre-amplifier module based on programmable gain amplifier and attenuator achieves gain from -26.2 dB to 24.4 dB, making it suitable to adapt to different detectors. Taking advantage of high speed and high-resolution analog-to-digit converter (ADC), the waveform digitization module samples the signal after conditioning with 12 bits resolution and up to 3.6 giga hertz samples per second (GSPS). To evaluate the feature of this instrument, an electronics testbench platform was installed and test results showed a bandwidth from direct current (DC) to 450 MHz and the effective number of bits (ENOB) is above 7 bits in high gain set and 5.8 bits in low gain set in the bandwidth range, which indicated that it had broad application prospect in detector calibration.