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Asymmetric chip placement and initial die-attach defects within a multichip IGBT power module (MIPM) can cause uneven junction temperature distribution and further accelerate the solder layer degradation. This is one of the main factors which affect the performance and reliability. This study uses the auxiliary emitter voltage veE to indirectly measure the turn-on delay time and the maximum rate of change of the collector current. The physical significance of the virtual junction temperature extracted from the two measurands is clarified. The correspondence between the veE and the degradation level of the solder layer is established using the difference between the two estimated temperatures. A novel condition monitoring method is then proposed in this article to identify the degradation level of individual solder layers using veE, which separates the effects of solder layer fatigue and bonding wires lift-off. The current dependence of the proposed method is negligible. Simulation and experimental results indicate that the proposed method can sensitively detect the highest degradation level of the chip in a MIPM in real-time.

Enhanced insulation and superior thermal characteristics are crucial in advanced packaging for medium voltage (MV) silicon carbide (SiC) power modules. Nonetheless, the reduction in thermal resistance typically compromises insulation level due to the decreased number of insulation layers. In this paper, the forced fluorinated liquid cooling is proposed, whereby fluorinated liquid (3M FC-40) is directed into the power module, substituting silicone gel and diminishing thermal resistance. Through the utilization of forced fluorinated liquid cooling, a reduction of 21°C in junction temperature at full load is demonstrated in the experiment, compared to traditional water cooled power modules. Furthermore, there is a 35.6% reduction observed in the maximum temperature rise ΔTj. As dissipation power is transferred from the topside of the chip to the fluorinated liquid, the possibility of unlimited stacking of direct bonded copper (DBC) is enabled to lower the electrical field, thereby facilitating insulation at the chip bottom side without any worries regarding heightened thermal resistance. Forced fluorinated liquid cooling resulted in a 39°C reduction in the double-stacked DBC power module. Moreover, partial discharge (PD) detection under square wave revealed that the DBC immersed in the fluorinated liquid remains free from PD at 10 kV, a significantly higher threshold than observed with silicone gel. A higher partial discharge inception voltage (PDIV) is anticipated for double-stacked DBC when immersed in 3M FC-40. Thus, the forced fluorinated liquid cooling can be considered a promising solution for the next generation of MV SiC power modules.

The medium voltage (MV) silicon carbide (SiC) power modules hold significant promise as a route for the solid-state converters to achieve higher power density, higher switching frequency, and lower loss. However, the emergence of partial discharge (PD) in the MV SiC power modules has posed a formidable challenge to enhancing its nominal voltage. In this article, a comprehensive review and comparative analysis of characterization, mitigation, and detection of PD under the square wave excitation is proposed for MV SiC power modules. First, the mechanism, detriments, and characterization of the PD issue and electrical tree in the MV power module are insightfully demonstrated. Meanwhile, the challenges from the PD for the MV SiC power module are emphasized. Besides, the geometric modification of direct bonded copper (DBC) structures to mitigate the PD issue is reviewed in detail. The limitations of the customized DBC are analyzed, considering the cost, reliability, and thermal resistance. Additionally, advanced dielectric materials are introduced and categorized. It is indicated that the effectiveness of the new dielectric under the square wave excitation stress still needs further investigation. Meanwhile, the optical, electromagnetic, electrical, and ultrasound detection methods under square wave excitation are further reviewed to assess the PD behavior in the MV SiC power module. Finally, suggested future researches for MV SiC power module packaging are proposed, aiming to inspire new ideas to further promote the insulation level of the MV SiC power module.

This article proposes a new power electronic packaging for discrete dies, namely, a standard cell, which consists of a step-etched active metal brazing (AMB) substrate and a flexible printed circuit board (flex-PCB). The standard cell exhibits high thermal conductivity, complete electrical insulation, and low stray inductance, thereby enhancing the performance of SiC mosfet devices. The standard cell has a stray power loop inductance of less than $\text{1}\,\text{nH}$ and a gate loop inductance of less than $\text{1.5}\,\text{nH}$. The standard cell has a flat body with surface-mounting electrical connections on one side and direct thermal connections on the other. The use of flex-PCB die interconnection enables maximum utilization of source pads while providing a flexible gate-source connection and the converter PCB. This article presents the design concept of the standard cell and experimentally validates its effectiveness in a converter system.

Coefficients of thermal expansion (CTE) of various materials in packaging structure layers vary largely, causing significant thermomechanical stress in power electronic packages during operation. For wirebondless SiC modules, the stress is even larger due to the structure's rigidity and the high Young's modulus of SiC crystals. This letter takes a flexible printed circuit board (FPCB)/die/active metal brazed (AMB) packaging stack as an example to prove the feasibility of floating die structure enabled by liquid metal (LM) fluidic connection. The CTE mismatch among the die, printed circuit board, and AMB substrate is decoupled by the LM layer without compromise of thermal and electrical conduction. The finite-element analysis demonstrates a 56% reduction in von Mises stress of the device and more than 99% shear stress reduction at the FPCB-AMB interface, compared with a conventional rigid solder connection. Testing results show that LM-based packaging has a similar thermal and electrical conduction and higher breakdown voltage when compared with the soldered counterpart. Accelerated thermal cycling aging tests validate the stability of the insulation ring for LM-based packaging, especially under high-temperature conditions. The feasibility of using LM fluidic interconnections for a floating die structure of SiC packaging is validated.

Reducing the thermal resistance is vital for power modules. Thermal conducting paths are formed by heterogeneous layers for insulation, causing inevitably high thermal resistance. In this article, with the aid of direct metallization technology, a direct bonded copper (DBC)-free power module concept is proposed to achieve near-junction water cooling. A 55% reduction of thermal resistance is achieved by using a DBC-free power module instead of a DBC interface. Reliability analysis indicates that the DBC-free power module is sufficiently reliable in terms of mechanical stress, fatigue, and peel strength. The junction temperature of the DBC-free power module is experimentally compared to indirectly and directly water-cooled power modules with the DBC interface. The proposed near-junction water cooling method has effectively achieved reductions of 28 °C and 11 °C in junction temperature, respectively, under full load conditions when compared to the designs of indirectly and directly water-cooled power modules. The maximum junction temperature rise ΔTj of the indirectly water-cooled power module is reduced from 50 °C to 21 °C. The unlimited promise of direct metallization technology in 3-D packaging is also highlighted.

This article motivates the loss characterization and modeling of Class II multilayer ceramic capacitors (MLCCs), which have been widely utilized owing to high energy density, in high-frequency resonant converters. In a resonant tank, MLCCs experience complex electrical operating conditions (e.g., large-signal, high-frequency, dc bias), but the incurred power loss has not been clearly characterized and modeled. This article first proposes a novel resonant-Sawyer–Tower circuit, which can experimentally extracts the loss of an MLCC in real operation in a resonant tank. A general loss modeling approach named Steinmetz's pre-electrified graph (SPeG) is then proposed to correlate capacitor's loss to the peak value of excitation, frequency, and dc bias voltage. The SpeG model provides the material-specific volume loss density of common class II dielectric materials and can be easily extrapolated to evaluate the loss of the MLCCs with different rated voltage and capacitance but employing the same dielectric material. To generalize the material-specific SPeG model to device-level application, this article also proposes an easy-to-follow tool, dielectric thickness observer (DTO), to estimate the internal microstructural geometry by tracking the $C$-$V$ characteristic provided in product datasheet. The synergy of the proposed characterization circuit, SPeG loss model, and DTO establishes a toolkit that enables the estimation of MLCC losses in a manner similar to that of a ferromagnetic inductor/transformer core. This article is accompanied by microscope images of the investigated MLCC samples and MATLAB scripts of the proposed DTO.