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Memory corruption vulnerabilities can lead to software attacks. Pointer-based memory safety protection has been shown as a promising solution covering both out-of-bounds and use-after-free errors. Software only approaches have significant performance overhead. Existing hardware/software implementations are largely limited to proprietary closed-source microprocessors, simulation-only studies or require changes to the input source code.In this paper, we present a novel hardware/software co-design methodology consisting of a RISC-V based processor extended with new instructions and microarchitecture enhancements, enabling faster memory safety checks. A compiler is instrumented to provide security operations taking into account the changes to the processor. The entire system is realized by enhancing a RISC-V Rocket-chip system-on-chip (SoC)1. The resultant processor SoC is implemented on an FPGA and evaluated with applications from SPEC 2006 (for generic applications), MiBench (for embedded applications), and Olden benchmark suites for performance. Our experiments show that the proposed approach achieves up to 3. 79X speedup (average 2. 6X) in comparison to the traditional software-based approach for SPEC2006 while possessing an overhead of 6.33% in terms of area. This speedup is better than the state-of-the-art approach. Our security coverage using the NIST Juliet test suite shows better coverage than the software only method.

Resection of infiltrating brain tumors, such as diffuse gliomas, generally involves resecting a portion of a lobe of the brain. While the concept of localized functions, and the risk to removing these areas, is well established in neurosurgical thinking, the potential that the overall global efficiency of the connectome could be disproportionately disturbed by an intervention in ways which are not immediately obvious have not been formally studied. The current article provides evidence that structural patterns exist in the impact resection of various lobes of the brain has, which also differs between subjects. We utilized diffusion tractography to create structural connectivity graphs from the brains of 80 healthy adults, and then performed every plausible brain surgery in every gross anatomic region of the cerebrum by deleting every possible combination of nodes in the graph which were adjacent to each other, and measured the drop in global efficiency (GE) at each nodal deletion. Not surprisingly, the deletion of some nodes was worse than others, such that in every lobe we studied in every subject, there were combinations of deletions which were worse for GE than removing a greater number of nodes in a different part of the brain. Interestingly, while the worst nodes differed between subjects, there were specific nodes which typically showed up as particularly detrimental regardless of which node was the worst in that person, but that there were patterns of so-called ―connectotype, which could determine which nodes were the worst. Progressive removal of a lobe of the brain leads to patterns of global efficiency decline which are reasonably predictable, but which are not the same between subjects. Given evidence that global efficiency relates to specific neuro-cognitive abilities, this provides a path towards reducing the cognitive footprint of brain surgery.

The cache memory has been a predominant component in modern chips, easily taking up more than 50% of the silicon area. It is then desirable to make the cache memory flexible for different needs. Therefore, many modern processor chips allow users to configure a part of the cache memory as the scratch-pad memory (SPM), a high-speed internal memory for rapid data access. However, such approach uses only the data RAM of the cache memory while leaving the tag RAM unused and thus wasting its capacity. This paper presents a cache organization, called Tag-SPM architecture, which allows the tag RAM to be used as the SPM and thus increases its capacity. It is accomplished with small Tag/Data-SPM controllers and four additional multiplexers in the cache organization. The proposed Tag-SPM architecture has been implemented with an academic ARM-based microprocessor with 4-/4-kB four-way set-associative instruction/data caches at the register transfer level level. Experiments show that the proposed architecture boosts the SPM capacity by 12.5% and requires only 0.08% area (434 gates) overhead without impairing the cache’s circuit speed in TSMC’s 90-nm standard cell implementation. Furthermore, the power overhead is negligible. When the Tag-SPM architecture is applied to typical cache systems, such as in ARM’s Cortex-A5 and Cortex-A53 processors, additional 12.5% SPM space per way can also be gained in both cases. The analyses show that our Tag-SPM architecture is a highly cost-effective way to boost the SPM space.

The magnetic properties and microstructure of FePt films grown on MgTiON intermediate layer were studied. The MgTiON layer was deposited by sputtered (MgTi)ON target at 395 °C. The MgTiON (002) texture was formed on CrRu (002)/glass. Furthermore, the 10 nm thick FePt film was deposited on MgTiON at 450 °C. The FePt shows perpendicular magnetization with out-of-plane coercivity of 3.62 kOe. Smaller FePt out-of-plane coercivity may come from lower ordering degree and continuous layer structure, which provides easy domain wall motion. To promote the ordering of FePt film, thinner MoC layer with thickness of 1 to 3 nm was capped on MgTiON (30 nm) layer during sputtering process. The FePt films with thickness from 4 to 10 nm show perpendicular magnetic anisotropy and the out-of-plane coercivities were increased to 11.9–15.3 kOe. The significant change of FePt out-of-plane coercivity was explained by ordering degree and microstructure. The island growth was dominated when FePt film prepared on thinner MoC interface and the excess carbon from MoC layer was diffused up to promote the ordering of FePt during sputtering. As a result, higher FePt out-of-plane coercivity on MoC/MgTiON intermediate layer was due to higher ordering degree and domain wall pinning effect in separated FePt islands.

The magnetic properties and microstructure of FePt films grown on MoC layer and MoC/(Mg–X)O (X=Cu, Ni, Co) combined intermediate layers were studied. The (Mg–X)O (X=Cu, Ni, Co) layer with thickness of 5 nm was deposited on CrRu seed layer at 395 °C. The CrRu (200) texture was enhanced which may due to well grains growth in specific orientation and small lattice mismatch with (Mg–X)O (X=Cu, Ni, Co). Finally, the FePt/MoC layers were deposited on (Mg–X)O layer at 425 °C. Using MoC/MgCuO combined intermediate layers, the rocking width of FePt (001) and CrRu (200) diffraction peak were changed from 7.1° to 6.1°, and 5.7° to 3.8°, respectively. For MoC/MgCoO dual intermediate layers, the rocking width of FePt (001) and CrRu (200) diffraction peak were 6.7° and 4.1°. The FePt/MoC/MgCoO film illustrates perpendicular magnetic anisotropy with out-of plane coercivity of 9.3 kOe which is higher than FePt film deposited on MoC layer (8.5 kOe) and the in-plane loops is linear. From microstructure, the FePt grains were more separated on MoC/(Mg–X)O (X=Cu, Ni, Co) combined intermediate layers.

In this paper, we present a bionic sensing system that monitor electromyography (EMG), electrocardiogram (ECG), vibration, and temperature for elderly care. The bionic sensor system contains analog front-end circuits (AFE) including sensor read-out circuit for bio-potential signal pickup, a piezo wave sensing circuit for vibration sensing, a low-power analog-to-digital (ADC) circuit with pulse-width modulation (PWM) digital signal output and a bandgap circuit for temperature tracking. For digital signal processing, we integrated a digital signal controller for AFE control and calibration, an ARM-like microprocessor (SYS32TM) for compression and communication. Finally, a phase-lock loop (PLL) circuit for system clock generating and power on reset, The analog and digital part of the chip has been tape-out separately. Analog circuit is integrated and tested with Xilinx Zynq System-on-Module (SoM). This verification platform is versatile for development while maintaining small form factor for user to wear the system while recording the bio-signals. The sensor system is currently used in elderly care and precision sport study.