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Two-dimensional (2D) metal oxides have aroused increasing attention in the field of electronics and optoelectronics due to their intriguing physical properties. In this review paper, an overview of recent advances on synthesis of 2D metal oxides and their electronic applications is presented. First, the tunable physical properties of 2D metal oxides that related to the structure (various oxidation-state forms, polymorphism, etc.), crystalline and defects (anisotropy, point defects, and grain boundary), and thickness (quantum confinement effect, interfacial effect, etc.) are discussed. Then, advanced synthesis method for 2D metal oxides besides mechanical exfoliation are introduced and classified into solution process, vapor phase deposition, and native oxidation on metal source. Later, the various roles of 2D metal oxides in widespread applications, i.e., transistors, inverters, photodetectors, piezotronics, memristors, and potential applications (solar cell, spintronics and superconducting devices) are discussed. Finally, the outlook of existing challenges and future opportunities in 2D metal oxides are proposed. This article is protected by copyright. All rights reserved.

In this work, an experiment was carried out to investigate the preparation condition of anisotropic Fe-deficient M-type Ca–Sr–La system ferrite with optimum magnetic and physical properties using the raw material Fe2O3 from steel industrial iron oxide waste. The compositions of the calcined ferrites were chosen according to the stoichiometry ${\mathrm {Ca}}_{1-x-y}$ La x Sr y Fe10.9CozO19, where M-type single-phase calcined powder was synthesized with a composition of $x = 0.45$ , $y = 0.18$ , and $z= 0$ . The effect of CaO, SiO2, and Co3O4 inter-additives on the Ca–Sr–La system ferrite was also discussed in order to obtain low-temperature sintered magnets. The magnetic properties of $B_{r} = 4570$ Gauss, $_{b}H_{c} = 4320$ Oe, $_{i}H_{c} = 5260$ Oe, and ( $BH$ ) $_{\mathrm {max}}= 5.16$ MGOe were obtained for Ca–Sr–La system hard magnets with low cobalt content at 1.85 wt%. The magnetic properties of the prepared magnets really good compared to that of the traditional Sr–La–cobalt (Co) M-type ferrite, which has been the highest grade M-type hard ferrite. The remarkable steel industrial iron oxide waste Fe2O3 is recycled to produce high-end permanent magnets under an output power of < 1 kW, which will eventually be used in high-efficiency motors.

In this study, we investigated the stress and doping effects of ferroelectric hafnium zirconium oxide (HfZrO) based on material analysis and electrical characteristics. The experimental results revealed that the ferroelectric crystalline phase is effectively transferred by mechanical stress of tantalum nitride (TaN) electrodes, and the origin of stress is mainly the thermal residual stress formed near the TaN and HfZrO interface. The ferroelectric polarization characteristics of HfZrO can be further modified by additional Al doping, which not only improves the leakage current of HfZrO due to the large bandgap of Al2O3 but also simultaneously stabilizes the ferroelectric domain switching under a large coercive field.

In this work, we investigate the ferroelectricity of stacked zirconium oxide and hafnium oxide (stacked HfZrO) with different thickness ratios under metal gate stress and simultaneously evaluate the electrical reliability of stacked ferroelectric films. Based on experimental results, we find that the stacked HfZrO films not only exhibited excellent ferroelectricity but also demonstrated a high performance on reliability. The optimized condition of the 45% Zr proportion exhibited a robust ferroelectric polarization value of 32.57 μC/cm2, and a polarization current with a peak value of 159.98 μA. Besides this, the ferroelectric stacked HfZrO also demonstrated good reliability with a ten-year lifetime under >−2 V constant voltage stress. Therefore, the appropriate modulation of zirconium proportion in stacked HfZrO showed great promise for integrating in high-performance ferroelectric memory.

We report the temperature effects on the performance of ferroelectric field-effect transistor (FeFET)-based non-volatile memory (NVM) considering random grain phase variation in the ferroelectric layer through simulation. Based on the FE temperature effect model that accounts for both the transistor and ferroelectric degradation, we demonstrate that: (1) at a certain temperature, the memory window (MW) decreases with pronounced effect on low threshold voltage shift and its variation increases as the FE phase decreases; (2) with the temperature increases, the MW decreases with pronounced effect on high threshold voltage shift. The random grain phase variation further exacerbates the MW distribution, thus degrading the sensing margin. These results may provide insights for device design of high-performance FeFET-based NVMs.

In this study, the impact of interfacial charges including fixed charges and acceptor-type traps between the dielectric and the channel in negative capacitance ferroelectric FETs (FeFETs) is investigated by simulation based on the Landau–Khalatnikov model. The results reveal the separate impact of the fixed charges and acceptor-type traps on device performance degradation, respectively, including the subthreshold swing (SS), switching current (I on and I off) and threshold voltage (V T). On this basis, the combined impact of interfacial charges with the fixed charges and acceptor-type traps co-existing equally is further explored. Our findings indicate that the fixed charges play a key role in the V T and I off, while the acceptor-type traps predominate in the SS and I on. This study helps to understand the degradation mechanism of FeFETs and extend the device end-of-lifetime.

The substantial amount of data generated every second in the big data age creates a pressing requirement for new and advanced data storage techniques. Luminescent nanomaterials (LNMs) not only possess the same optical properties as their bulk materials but also have unique electronic and mechanical characteristics due to the strong constraints of photons and electrons at the nanoscale, enabling the development of revolutionary methods for data storage with superhigh storage capacity, ultra-long working lifetime, and ultra-low power consumption. In this review, we investigate the latest achievements in LNMs for constructing next-generation data storage systems, with a focus on optical data storage and optoelectronic data storage. We summarize the LNMs used in data storage, namely upconversion nanomaterials, long persistence luminescent nanomaterials, and downconversion nanomaterials, and their applications in optical data storage and optoelectronic data storage. We conclude by discussing the superiority of the two types of data storage and survey the prospects for the field.

In this paper, we investigated the performance of an n-type tin-oxide (SnOx) thin film transistor (TFT) by experiments and simulation. The fabricated SnOx TFT device by oxygen plasma treatment on the channel exhibited n-type conduction with an on/off current ratio of 4.4×104, a high field-effect mobility of 18.5 cm2/V.s and a threshold swing of 405 mV/decade, which could be attributed to the excess reacted oxygen incorporated to the channel to form the oxygen-rich n-type SnOx. Furthermore, a TCAD simulation based on the n-type SnOx TFT device was performed by fitting the experimental data to investigate the effect of the channel traps on the device performance, indicating that performance enhancements were further achieved by suppressing the density of channel traps. In addition, the n-type SnOx TFT device exhibited high stability upon illumination with visible light. The results show that the n-type SnOx TFT device by channel plasma processing has considerable potential for next-generation high-performance display application.

Inexpensive and flexible organic resistive memory can be easily fabricated, scaled and stacked. Owing to these advantages, organic resistive memory is considered as a very promising technology capable of substituting current inorganic semiconductor-based memory technology. It has attracted a lot of attention from the scientific and engineering communities. In this mini-review, the recent state-of-the-art developments related to organic small molecules for resistive random-access memory (RRAM) have been emphasized. We first describe the general characteristics of RRAM devices, their typical structures, fabrication, classification, and switching mechanisms. Next, we discuss the usage of RRAM devices in next-generation computing. In particular, we discuss the use of organic small molecules and their composites in RRAM with various functionalities. Finally, the current challenges and developing trends of performance improvement for organic small molecule-based RRAM are discussed.

Fabrication, physical modeling and dynamic response of p-type Al-doped SnOx active channel thin film transistors (TFTs) are presented for the potential application of ultra-high definition (UHD) displays. After deposition of Al-doped SnOx active layer using reactive co-sputtering, the channel was treated with plasma fluorination which improve the device performance of high ION/IOFF ratio of > 106, low subthreshold swing of ~100 mV/dec and high field-effect mobility (μFE) of 4.8 cm2V-1s-1. To understand the origin of such high performance, physical modeling and numerical simulations were performed using density of state (DOS) model of defects/traps of oxide semiconductor. This model describes the modifications of donor-like tail states and acceptor-like Gaussian defect states due to Al doping on SnOx and fluorine treatment. To evaluate the device performance for UHD large scale displays, the dynamic responses of p-type TFT pixel circuit for various requirements are simulated with physical models. These results suggest that the Al-doped SnOx TFTs are potential candidates for future high-definition displays and many applications in transparent electronics.

Transparent electronics has attracted much attention and been widely studied for next-generation high-performance flat-panel display application in the past few years, because of its excellent electrical properties. In display application, thin film transistors (TFTs) play an important role as the basic units by controlling the pixels. Among them, oxide-based TFTs have become promising candidates and gradually replaced the conventional amorphous and polycrystalline silicon TFTs, due to high mobility, good transparency, excellent uniformity and low processing temperature. Even though n-type oxide TFTs have shown high device performance and been used in commercial display application, p-type oxide TFTs with the equal performance have been rarely reported. Hence, in this paper, recent progress and challenges in p-type oxide-based TFTs are reviewed. After a short introduction, the TFT device structure and operation are presented. Then, recent developments in p-type oxide TFTs are discussed in detail, with the emphasis on the potential p-type oxide candidates as copper oxide, tin oxide and nickel oxide. Moreover, miscellaneous applications of p-type oxide TFTs are also presented. Despite this, the performance of p-type oxide TFTs still lags behind, as compared with that of n-type counterparts. Thus, the current issues and challenges of p-type oxide TFTs are briefly discussed.

Optimal device integrity was achieved in Ni/SiGeOx/TiOy/TaN resistive memory by using a forming-free switch with a low switching power of 790 μW, stable endurance of 104 cycles, optimal retention time of 105 s, resistance window of at least 1150×, and tight current distributions at 85 °C. These characteristics are attributed to the low current switching obtained using SiGeOx with a high oxygen vacancy density and highly defective TiOy grain boundaries.

In this paper, the effect of channel annealing and oxygen flow rate in P-type tin-monoxide (SnO) thin film transistor (TFT) was investigated to reach the process compatibility with n-type oxide-based TFT. The optimized P-type SnO TFT with a small threshold voltage of -0.1 V, a high field-effect mobility of 4 cm² V-1 s-1 and an on/off current ratio of >10² was proposed. From the experimental results, the 150 °C channel annealing revealed a metallic behavior but a semiconductor-like property at a higher 200 °C that was favorable for transistor rectification. Besides, the higher oxygen flow rate was also helpful for improving device mobility and driving current, but shows a slight increase in off-state leakage, which is unavoidable due to the increase of grain in SnO channel.

In this work, we successfully demonstrated the 9.6-nm-thick HfAlOx ferroelectric memory using light aluminium doping of 6.5% to form ferroelectric orthorhombic phase. Compared to ferroelectric HfZrOx film with zirconium diffusion issue, the HfAlOx film showed excellent thermal stability under high temperature annealing. Besides, the ferroelectric HfAlOx also exhibited robust polarization characteristics under endurance cycling test. A >106 stressed cycles with 4 MV/cm can be measured and a long endurance was sustained over 5 × 107 cycles under 3.6 MV/cm. Therefore, the HfAlOx film showed the great promise for integrating in high performance ferroelectric memory with thermal budget concerns.

With experimental and numerical simulation, we report the origin of the performance enhancement in p-type SnO thin-film transistors (TFTs) due to fluorine plasma treatment (FPT). To study the effect of fluorination, using the reactive-ion-etching process, the devices are treated at various plasma powers upto 60 W. It is observed, through X-ray photoelectron spectroscopy and XRD measurements, that the plasma fluorination modifies the defect/trap states of SnO channel and SnO/HfO2 interface. These effects are introduced through density of state (DOS) model for SnO in numerical simulations, to understand the routes of electrical performance improvement. It is observed that the attributes of donor-like band-tail state and acceptor-like Gaussian defect states (Sn vacancies) are modified in overall DOS due to plasma fluorination. The treated device shows excellent electrical performances with high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~107 and low substhreshold swing of ~ 100 mV/dec and field-effect mobility ( $\mu _{\text {FE}}$ ) of 2.13 cm2V−1s−1.

In this paper, we reported a ferroelectric HfAlO x negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlO x transistor with GS engineering percentage of $\text{I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement and 27% $\text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node.

In this work, we studied the temperature dependences of endurance cycling properties on atomic layer deposition (ALD) HfAlO metal-ferroelectric-metal (MFM) capacitor in the range from 25 °C, 40 °C, 50 °C and 75 °C. Base on experiment results, it is found the reduction percentage of the ferroelectric memory window (2Pr) from 6.5 μC cm−2 (25 °C) to 6.3 μC cm−2 (75 °C) is only 3%, indicating that the ferroelectric HfAlO film has a robust operating temperature stability. The excellent high temperature endurance properties show around 30% of the original 2Pr value (6.3 μC cm−2) can be held after being fatigued up to 108 endurance cycles at 75 °C without breakdown. Additionally, using Arrhenius plot fitting (ln(J/E) vs 1/kT) before and after endurance cycles was extracted the changes of trapping energy level to better understand the relationship between leakage current, oxygen vacancies or defects tapping of polarization-switching behavior in HfAlO ferroelectric film.

In this work, an experiment was carried out to investigate the preparation condition of anisotropic, Fe-deficient, M-type Sr ferrite with optimum magnetic and physical properties by changing experimental parameters, such as the La substitution amount and little additive modification during fine milling process. The compositions of the calcined ferrites were chosen according to the stoichiometry LaxSr1-xFe12-2xO19, where M-type single-phase calcined powder was synthesized with a composition of x = 0.30. The effect of CaCO3, SiO2, and Co3O4 inter-additives on the Sr ferrite was also discussed in order to obtain low-temperature sintered magnets. The magnetic properties of Br = 4608 Gauss, bHc = 3650 Oe, iHc = 3765 Oe, and (BH)max = 5.23 MGOe were obtained for Sr ferrite hard magnets with low cobalt content at 1.7 wt%, which will eventually be used as high-end permanent magnets for the high-efficiency motor application in automobiles with Br &gt, 4600 ± 50 G and iHc &gt, 3600 ± 50 Oe.

In this study, the preparation and magnetic properties of Ca–Sr M-type (Ca1-x-yLaxSryFe10.9CozO19) ferrire magnets were investigated. A M-type singlephase calcined powder was synthesized with a composition of x ​= ​0.45, y ​= ​0.18 and z ​= ​0. And a very high magnetic properties of Br ​= ​5425Gauss and iHc ​= ​4602Oe were obtained by the thermal annealing and secondary fine-milling method in the sintered magnets. The magnetic properties greats exceeds that of traditional Sr–La–Co M-type ferrite, which has been the highest grade M-type hard ferrite. By use of the innovative post-processing method, the improvement could be attributed to about 4% and 0.8% increase in motor torque and motor efficiency in comparison to that of conventional process, which will eventually be used in high-efficiency motors.

In this study, we reveal that the thermal budget of post-metal annealing not only determines the formation of the ferroelectric phase and dipole domain but also the film quality of the gate stack in a metal-ferroelectric-metal capacitor. The higher leakage current caused by defect traps or grain boundaries within a gate stack would influence the stability of the ferroelectric domain switching. Furthermore, the ferroelectric domain switching and polarization current also depend on the ferroelectric capacitor area. We observe that a HfAlO ferroelectric capacitor can dominate the transfer characteristics of a p-type SnO thin-film transistor through the modulation of series capacitance in the gate stack based on a one-transistor one-capacitor series configuration. According to experimental results, the memory hysteresis window can be improved significantly with the area scaling due to the improvement of capacitance matching accuracy.

For the first time, we successfully demonstrated the dopant-free HfO2 negative capacitance (NC) transistor featuring a low gate-overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. These excellent performances can be ascribed to the reduction of the monoclinic phase suppressed with the thickness scaling and gate stress engineering favorably rearranging oxygen vacancies to boost orthorhombic phase transition. The highly scalable and dopant-free NC transistor shows the potential for the application of advanced CMOS technology.

In this work, the influence of the time points of the simultaneous or separate partial substitution of La3+ for Sr2+ and of Co2+ for Fe3+ in Sr ferrite on the magnetic properties of anisotropic M-type Sr ferrite magnets was investigated. It was found that the optimum values of the remanence Br and of the coercivity Hci of Sr ferrite magnet were obtained by La-Co simultaneous substitution before calcination. On the other hand, Hci is increased with causing minor decrease in Br by La separate substitution before calcination and Co separate substitution after calcination. Whereas, La-Co simultaneous substitution after calcination has a deteriorating effect on the Br of M-type Sr ferrite. Optimum magnetic properties and conditions in the experiment will eventually be used as high-end permanent magnets for the high-efficiency motor application in automobile with Br > 4500 ± 50 Gauss and Hci > 4500 ± 50 Oe.

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.

In this study, we demonstrated a p -type and n -type SnO TFTs on flexible polyimide substrate. The fabricated p -type SnO TFT showed a high $I_{\rm on}/ I_{\rm off}$ of $ \text{5.7}\, \times \,\text{10}^{5}$ and a high $\mu _{{\rm{FE}}}$ of ${\text{10.7 cm}}^{2}\,{\text{V}}^{-1}\,{\text{s}}^{-1}$ . Through optimizing the oxygen plasma condition, the n -type channel TFT transfered from prime p -type channel exhibits excellent characteristics, including a high on/off current ratio of $\rm{6.6}\,\times\,10^{3}$ , a low threshold voltage of −0.13 V, and a very high field-effect mobility of ${\text{28 cm}}^{2}\,{\text{V}}^{-1}\,{\text{s}}^{-1}$ . This proposed low-temperature oxygen plasma treatment shows the potential in simplification of TFT process that can achieve n -type and p -type TFTs under the same device process.

Optimal device integrity was achieved in Ni/SiGeO

We demonstrated that the 2.5nm-thick HfAIO x N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing $(SS)$ , a negligible hysteresis of 1mV, an ultralow $I_{off}$ of $135\ \text{fA}/\mu \text{m}$ , a large $I_{on}/I_{0ff}$ ratio of $8.7\times 10^{7}$ and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAIO x CMOS NCFET shows the potential for low power logic applications.

In this paper, we experimentally demonstrated the advantage of remote nitrogen plasma on improving interface quality of HfO2-based ferroelectric devices. The remote nitrogen plasma not only reduces leakage current of gate stack to appropriately sustain the ferroelectricity during ferroelectric domain switching, but also effectively improve the ferroelectric fatigue to enhance endurance cycling performance.

In this paper, the ferroelectric polarization effect of ZrO 2 capping layer on HfO 2 MFM capacitor was investigated. Based on crystallinity analysis, the phase transformation from monoclinic to orthorhombic phase in HfO 2 film can be induced by a thin ZrO 2 capping layer. The thickness of ZrO 2 capping layer plays an important role in the ferroelectric polarization of HfO 2 MFM capacitor. Compared to mixed HfZrO film, the stacked ZrO 2 /HfO 2 film shows the advantage for suppressing the leakage issue during hightemperature ferroelectric phase transition.

In this paper, we investigated the bipolar conduction mechanism in thin-film transistors (TFTs) with oxygen plasma treatment on tin-oxide channel. The optimized p-type thin-oxide TFTs showed an on/off ratio of ${>}{\hbox{10}}^{4}$ , a threshold voltage of $-$ 1.05 V, and a field-effect mobility of ${\hbox{2.14}}\ {\hbox{cm}}^{2}{\cdot}{\hbox{V}}^{-1}{\cdot}{\hbox{s}}^{-1}$ . By increasing the exposure time of oxygen plasma, excess oxygen was incorporated to thin-oxide channel and converted thin monoxide to oxygen-rich n-type thin dioxide, which in turn led to n-type operation. It indicated that oxygen plasma was the critical factor to determine oxygen concentration, oxygen vacancies, metal ions and channel polarity. This proposed oxygen-content tuning through plasma treatment approach shows great promise in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.

This paper reported the IGZO and IZO thin-film transistor (TFT) with titanium-oxide semiconductor as channel capping layer. After the ${\hbox{TiO}}_{x}$ Gettering process, the oxygen vacancies in IGZO channel were successfully modified to maximize the carrier concentration and device mobility. The superior transfer characteristics included a low sub-threshold swing of 79 mV/decade, a very high mobility of ${\hbox{68}}~{\hbox{cm}}^{2}/{\hbox{V}}{\cdot}{\hbox{s}}$ , and good on/off-current ratio of ${\hbox{5.61}}\times {\hbox{10}}^{6}$ . However, the IZO channel with nano-crystallized grains and without Ga atom doping showed unfavorable transistor characteristics. In addition to apparently degraded transfer properties, the spontaneously oxidized ${\hbox{TiO}}_{x}$ capping layer also lead to an increase of channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga–O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during Gettering process.

To understand the effect of deposition sequence of ferroelectric HfZrO, we investigated the ferroelectric polarization characteristics of a 50%-zirconium-doped HfZrO and a stacked HfZrO metal-ferroelectric-metal capacitors. Based on experimental results, we find that the leakage current can be effectively suppressed in stacked HfZrO film. The film stack structure is favorable for simultaneously stabilizing the ferroelectric polarization and minimizing the generation of interface defect traps during the post-metal annealing process with a thermal budget of 600 – 800 °C, which is favorable for complementary-metal-oxide-semiconductor frond- and back-end process integration with various thermal budget requirement.

The impacts of various tensile strains on both DC and RF performance of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) on a silicon-on-insulator (SOI) substrate were investigated using pulsed-IV and pulsed-S-parameter tests. The sensitivity of MIS-HEMTs to various tensile strains was observed via pulse measurements because of the improved self-heating effect. The DC and RF performance of MIS-HEMTs on a SOI substrate were found to be enhanced with the pulse width decreasing under small tensile strain. A significant hot phonon effect was observed for MIS-HEMTs under larger tensile strain, particularly for shorter pulse widths. Additionally, an obvious reduction of fmax was observed under larger tensile strain because the channel resistance increased via the hot phonon effect, despite the increase in ft. The results indicated that tensile strain in the ultra-thin thinned substrate of AlGaN/GaN HEMTs should be carefully monitored in compact packages for high-power and high-frequency applications.