Search

In this paper, a new color image compression algorithm based on Absolute Moment Block Truncation Coding (AMBTC) and entropy coding is proposed. The AMBTC improves the compression performance of Block Truncation Coding (BTC) obviously. A novel technique by using eight different types of bitmap tables is developed for the proposed algorithm. In addition, an entropy coding technique combining prediction and Huffman Coding approach is included in the proposed algorithm and decreased the data amount of luminance images. The experimental results show that more than 82% data amount can be compressed by using the eight different types of novel bitmap tables. Compared with previous studies, this work has better compression performance than previous 4*4 BTC, JPEG, and JPEG-LS algorithms.

Recently, intelligent automobile electronics, advanced driver assistance system (ADAS) and intelligent transport system (ITS) have become to make great strides towards to the goal of automatic driving and smart cities. Therefore, how to enhance the visibility no matter at night or excessive exposure turns into an important issue of the research. In this paper, a novel effective contrast enhancement and hardware-oriented algorithm is proposed. The proposed contrast enhancement algorithm includes a RGB to HSV module, a mirror expansion module, a weighted filter and a Gamma correction module. A new technique called weighted filter was used to pick up the best brightness factor for the proposed algorithm. To be suitable for VLSI implementation, the proposed algorithm was developed based on low-complexity and low-memory-requirement. Compared with previous studies, this work proposed a high quality and low complexity hardware-oriented contrast enhancement algorithm for VLSI implementation.

Well-defined experimental and simulating single peak to valley current density ratio (PVCDR) resonant tunneling electronic circuit (RTEC) element is proposed in this research. The variation of passive element value in RTEC structure is explored using simulation method, which obtains the optimum PVCDR values about 66. The simulating peak current density (PCD) value is such high as 38 mA. Even though the experimental PCD value is less, but the PVCDR value is as high as 22.5, which value is favorably compared with semiconductor resonant tunneling devices (RTDs) in single PVCDR RTEC element. The obvious triple negative differential resistance (NDR) is also completed using composition of three suitable single RTEC elements. Also, experimental triple PVCDR RTEC element significantly exhibits three NDR curves with obvious three PVCDR values about 3.4, 3.8, and 6.0, respectively. Both peak voltage (PV) value and valley voltage (VV) values of experimental triple PVCDR RTEC element is less than 2.8 V, which value is profitable in development of commercial product. Power consumption of triple PVCDR RTEC element is as low as 75.5 μW, which low power consumption will shrink the difficulty of element packaging in heat dissipation. DOI: http://dx.doi.org/10.11591/telkomnika.v10i6.1416 Full Text: PDF

Three similar negative differential resistance (NDR) profiles with both high peak to valley current density ratio (PVCDR) value and high peak current density (PCD) value in unity resonant tunneling electronic circuit (RTEC) element is developed in this paper. The PCD values and valley current density (VCD) values of the three NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR values reach about 4.4 in three NDR curves. The PCD value of 3.5 A in triple PVCDR RTEC element is better than other resonant tunneling devices (RTD) elements. The high PVCDR value is concluded the lower VCD value about 0.8 A. The low VCD value is achieved by suitable selection of resistors in triple PVCDR RTEC element. The low PV value less than 1.35 V possesses low power dispersion in triple PVCDR RTEC element. The designed multiple value logical level (MVLL) system using triple PVCDR RTEC element provides equidistant logical level. The logical levels of MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from high voltage back to low voltage in half cycle of sinusoid wave. The output level of four levels MVLL system is represented in 0.3 V, 1.1 V, 1.7 V, and 2.6 V, which satisfies the NMP condition of traditional two-bit system. The remarkable logical characteristic of improved MVLL system with paralleled capacitor are with four significant stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV. The stability and articulation of logical levels of improved MVLL system are outstanding. The average holding time of improved MVLL system is approximately 0.14 μs. The holding time of improved MVLL system is fourfold than of basic MVLL system. The function of additional capacitor in the improved MVLL system is successfully discovered., {"references":["O. T. Hanyu and M. Kameyama, \"A 200 MHz pipelined multiplier using\n1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail\nsource-coupled logic,\" IEEE Journal of Solid-State Circuits, vol. 30(11),\npp.1239-1245, Nov. 1995. Pages:1239 - 1245","N. Jin; S. Y. Chung, R. M. Heyns, P. R. Berger, Y. Ronghua, P. E.\nThompson, and S. L. Rommel, \"Tri-state logic using vertically integrated\nSi-SiGe resonant interband tunneling diodes with double NDR,\" IEEE\nElectron Device Letters, vol. 25(9), pp. 646-648, Sept. 2004.","R. Versari, D. Esseni, G. Falavigna, M. Lanzoni, and B.\nRicco,\"Optimized programming of multilevel flash EEPROMs,\" IEEE\nTransactions on Electron Devices, vol. 48(8), pp.1641-1646, Aug. 2001.","T. Temel and A. Morgul, \"Implementation of multi-valued logic,\nsimultaneous literal operations with full CMOS current-mode threshold\ncircuits,\" Electronics Letters, vol. 38(4), pp. 160-161, Feb 2002.","S. J. Piestrak and A. Dandache, \"Minimal test set for multi-output\nthreshold circuits implemented as bubble sorting networks,\" Electronics\nLetters, vol. 36(3), pp.202-204, Feb. 2000.","A. C. Seabaugh, E. A. Beam, A. H. Taddiken, J. N. Randall, and Y. C.\nKao, \"Co-integration of resonant tunneling and double heterojunction\nbipolar transistors on InP,\" IEEE Electron Device Letters, vol. 14(10) , pp.\n472-474, Oct. 1993.","K. J. Chen, K. Maezawa, and M. Yamamoto, \"InP-based\nhigh-performance monostable-bistable transition logic elements\n(MOBILEs) using integrated multiple-input resonant-tunneling devices,\"\nIEEE Electron Device Letters, vol. 17 (3), pp. 127-129, March 1996.","K. J. Gan and Y. K. Su, \"Novel multipeak current-voltage characteristics\nof series-connected negative differential resistance devices,\" IEEE\nElectron Device Letters, vol.19 (4), pp.109-111, April 1998.","W. C. Liu, L. W. Laih, S. Y. Cheng, W. L. Chang, W. C. Wang, J. Y.\nChen, and P. H. Lin,\"Multiple negative-differential-resistance (MNDR)\nphenomena of a metal-insulator-semiconductor-insulator-metal\n(MISIM)-like structure with step-compositioned InxGa1-xAs quantum\nwells,\" IEEE Transactions on Electron Devices, vol. 45(2), pp.373-379,\nFeb. 1998.\n[10] S. Villareal, M. Weichold, and J. Pineda, \"Simulation study of compact\nquantising circuits using multiple-resonant tunnelling transistors,\"\nElectronics Letters, vol. 34(2), pp.161-162, Jan. 1998.\n[11] J. L. Huber, J. Chen, J. A. McCormack, C. W. Zhou, and M. A. Reed,\"An\nRTD/transistor switching block and its possible application in binary and\nternary adders,\" IEEE Transactions on Electron Devices, vol. 44(12),\npp.2149-2153, Dec. 1997.\n[12] W. C. Liu, W. S. Lour, and Y. H. Wang, \"Investigation of AlGaAs/GaAs\nsuperlattice-emitter resonant tunneling bipolar transistor (SE-RTBT),\"\nIEEE Transactions on Electron Devices, vol. 39(10), pp.2214-2219,Oct.\n1992.\n[13] W. C. Liu, W. C. Wang, H. J. Pan, J. Y. Chen, S.Y. Cheng, K. W. Lin, K.\nH. Yu, K. B. Thei, and C. C. Cheng,\"Multiple-route and multiple-state\ncurrent-voltage characteristics of an InP/AlInGaAs switch for\nmultiple-valued logic applications,\" IEEE Transactions on Electron\nDevices, vol. 47(8), pp.1553-1559, Aug. 2000.\n[14] J. J. Blakley, \"Architecture for hardware implementation of\nprogrammable ternary de Bruijn sequence generators,\" Electronics\nLetters, vol. 34(25), pp. 2389-2390, Dec. 1998.\n[15] F. Toto and R. Saletti, \"CMOS dynamic ternary circuit with full logic\nswing and zero-static power consumption,\" Electronics Letters, vol.\n34(11), pp. 1083-1084, May 1998.\n[16] C. C. Yang, \"High Performance Multiple Stepped Quantum Well\nResonant Microwave Devices\", Electronics Letters, Vol. 42(25),\npp.1485-1487, December, 2006.\n[17] C. C. Yang and Yan Kuin Su,\"Well-defined electrical properties\nhigh-strain resonant interband tunneling structure\",Microelectronics\nJournal, vol.39(1), pp.67-69, January, 2008.\n[18] C. C. Yang and Yan Kuin Su,\" High Performance Aluminum Arsenic\nIntraband Resonant Microwave Devices\", Microelectronics Journal,\nvol.39(1), pp.90-93, January, 2008.\n[19] C. C. Yang,\" Frequency Computation of Resonant Signal in Resonant\nTunneling Circuit for Communication,\" 2010 Second International Joint\nJournal Conference on Computer and Communication Technology\n(IJJCCT 2010), Jeju Island, Korea 27-28 December 2010."]}