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Hollow dielectric waveguides (HDWs) are renowned for their extremely low-loss transmission among all dielectric -based solutions. Highly-integrated multilane HDWs are expected to be applied for increasing demand on high-throughput communication. Unfortunately, severe crosstalk and loosely confined electromagnetic field have been a critical issue for a long time. In this article, we demonstrate a novel 1-D photonic crystal fence. Photonic particles represent a series of guard lining up beside the waveguides. Over 30-dB crosstalk reduction can be realized for closely placed HDWs. This proposed method, without altering the original structure of HDWs, offers high degrees of freedom for the HDW design. The experimental results show good field confinement in the mm-wave range, but not limit to it. This all-dielectric -based solution implies its opportunity for subterahertz to optical frequency application. Moreover, photonic crystal fence with only 1-D arrangement makes this concept feasible for both tubular HDWs and other planar integrated dielectric -based waveguides on board. This technique takes a key step for highly integrated multilane HDWs in the near future.

Traditional heterogeneous integrated package structure actually uses several complete IC packages, while the final heterogeneous integrated package structure is completed by restacking and packaging of various IC packages. However, the relatively large package volume, low-density interconnections and low circuit density cannot meet the demand for lighter products. There are still many issues remained in the heterogeneous integration process due to the fact that each chip has its own chip size, material properties, and device type. In order to integrate various heterogeneous chips, a new chip stacking technology is necessary to simplify and reduce the packaging structure, which is used for multi-chip and multi-layer heterogeneous integrated packaging structures as well as obtaining high performance and high bandwidth density. A novel EIC (Embedded interposer carrier) heterogeneous integrated packaging technology is developed to provide SOC-like multi-layer and multi-chip stacking capabilities, which is similar to chiplet concept. In this work, a 21-mm × 14-mm interposer is embedded into an electric package, allowing the interposer to work as a bridge between the two chips, and to provide high-density and high-pin-count interconnects. The external dimension of these two chips is 9 mm × 9 mm and the chip thickness is 100µm. The electrical performance including the power integrity/signal integrity analysis was evaluated by designed test patterns. Daisy chain and Kelvin structure were also included in the testing structure. This new packaging structure is compatible with fan-out packaging technology and enables integration for different chips in order to achieve performance related to 3D IC with a low cost.

Fan-out wafer-level packaging (FOWLP) has evolved from chip-scale packaging to be one of the enablers of heterogenous integration through chip-first or redistribution-layer (RDL)-first processes, which draw significant momentum in packaging industries to develop newer and better materials. Among all of the essential packaging materials currently being investigated, novel laser release materials are of particular interest because they are vital to the successful separation of reconstituted wafers and glass carriers. Thus, the thermal, chemical, and mechanical stability of the laser release material play a vital role for success in FOWLP integration. In this study, four laser release materials with UV-light absorbance were evaluated through experiments divided into two phases to select a champion material for chip-first and RDL-first FOWLP integration. Phase I consisted of the collection of material properties and characteristics including light transmittance, interaction with laser energy, thermal stability, adhesion, and melt rheology to determine compatibility with RDL-first and chip-first processes, respectively. In Phase II, all candidate laser release materials were introduced to a short-loop evaluation that started with a laser release material coating on 300-mm glass carrier with a coefficient of thermal extension (CTE) of 8 ppm/°C, followed by 50-nm titanium deposition, 100-nm copper deposition, and dielectric material coating before encapsulation with epoxy molding compound. Multiple 355-nm laser powers that created different diameters of effective ablation region inside the crater, were used to determine the sensitivity of each candidate material. Meanwhile, chips sized, were picked and placed on coated glass carriers with candidate laser release materials to evaluate the compatibility with the chip-first process. Finally, design of a die bonding experiment was used to summarize the optimal conditions of a laser release material, proved compatible with RDL-first in advance, for a chip-first process. Through the comprehensive material evaluation discussed in this study, optimal laser release materials for the RDL-first and chip-first processes are identified. Of particular interest are materials that possess both laser release properties and good adhesion, since their use in die bonding applications will enhance throughput and lower the cost of ownership for FOWLP.