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A one-band self-consistent effective mass approximation (EMA) for hole quantization in p-MOSFET is described and discussed.

Hole tunneling can be used to project the electrical oxide thickness scaling limit of the oxynitride/oxide gate stack dielectrics used in p-MOSFETs. The validity of the model is verified by the excellent agreement between the simulated and experimental results.

A model is proposed for examining hole-quanization effects in inversion layers of p-metal-oxide semiconductor (p-MOS) devices. It relies on a six-band effective mass equation and a zigzag potential.

Research describing the characteristics of gallium nitride thin films epitaxially grown on silicon substrates is presented. Infrared reflectance spectroscopy studies are analysed for optical and electronic properties of the thin films.

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO2 and HfO2 gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces: the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function ф β of a metal! gate affects tunneling characteristics in MOSFETS. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of ф β reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap ф β results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk YET, double gate (DG); VET1 has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-κ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed. [ABSTRACT FROM AUTHOR]