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In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware. Although previous approaches including these effects in model training successfully improved variation tolerance, they only considered part of the nonideal effects and relatively simple classification tasks. This paper proposes a joint hardware and software optimization strategy to design a hardware-robust IRC macro for object detection. We lower the cell current by using a low word-line voltage to enable a complete convolution calculation in one operation that minimizes the impact of nonlinear addition. We also implement ternary weight mapping and remove batch normalization for better tolerance against device variation, sense amplifier variation, and IR drop problem. An extra bias is included to overcome the limitation of the current sensing range. The proposed approach has been successfully applied to a complex object detection task with only 3.85\% mAP drop, whereas a naive design suffers catastrophic failure under these nonideal effects., Comment: 10 pages, 18 figures

In this paper, we present an efficient hardware mapping methodology for realizing vector matrix multiplication (VMM) on resistive memory (RRAM) arrays. Using the proposed VMM computation technique, we experimentally demonstrate a binarized-ADALINE (Adaptive Linear) classifier on an OxRAM crossbar. An 8x8 OxRAM crossbar with Ni/3-nm HfO2/7 nm Al-doped-TiO2/TiN device stack is used. Weight training for the binarized-ADALINE classifier is performed ex-situ on UCI cancer dataset. Post weight generation the OxRAM array is carefully programmed to binary weight-states using the proposed weight mapping technique on a custom-built testbench. Our VMM powered binarized-ADALINE network achieves a classification accuracy of 78% in simulation and 67% in experiments. Experimental accuracy was found to drop mainly due to crossbar inherent sneak-path issues and RRAM device programming variability., Comment: Accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 2020

Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU Memory is observed to be ~ 780x.

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit dataset to 87.8/94.8% by using 6-bit/8-bit analog synapses, respectively, with extremely high asymmetric nonlinearity., Comment: IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2017

Molybdenum ditelluride (MoTe$_2$) has attracted considerable interest for nanoelectronic, optoelectronic, spintronic, and valleytronic applications because of its modest band gap, high field-effect mobility, large spin-orbit-coupling splitting, and tunable 1T'/2H phases. However, synthesizing large-area, high-quality MoTe$_2$ remains challenging. The complicated design of gas-phase reactant transport and reaction for chemical vapor deposition or tellurization is nontrivial because of the weak bonding energy between Mo and Te. Here, we report a new method for depositing MoTe$_2$ that entails using physical vapor deposition followed by a post-annealing process in a Te-free atmosphere. Both Mo and Te were physically deposited onto the substrate by sputtering a MoTe$_2$ target. A composite SiO$_2$ capping layer was designed to prevent Te sublimation during the post-annealing process. The post-annealing process facilitated 1T'-to-2H phase transition and solid-phase crystallization, leading to the formation of high-crystallinity few-layer 2H-MoTe$_2$ with a field-effect mobility of ~10 cm$^2$/(V-s), the highest among all nonexfoliated 2H-MoTe$_2$ currently reported. Furthermore, 2H-MoS$_2$ and Td-WTe$_2$ can be deposited using similar methods. Requiring no transfer or chemical reaction of metal and chalcogen reactants in the gas phase, the proposed method is potentially a general yet simple approach for depositing a wide variety of large-area, high-quality, two-dimensional layered structures., Comment: Submitted version

We present a novel electronic-structure modulation transistor (EMT), which can possibly be used for post-CMOS logic applications. The device principle is based on the bandwidth modulation of a midgap or near-midgap localized state in the channel by a gate voltage. A single-band tight-binding method coupled with non-equilibrium Green's function formalism for quantum transport is employed to predict the IV characteristics. Our objective is to confirm if an EMT has a self gain and if it can overcome the 2.3kT/decade thermal limit with low supply voltage. The ON current depends on the bandwidth of the state and is limited by the quantum of conductance for a single band. The OFF current is set by the gate leakage and tunneling through the higher bands, which is expected to be small if these bands are a few eV above the energy level of the localized state.

We report a novel field-sensitive tunneling barrier by embedding C60 in SiO2 for nonvolatile memory applications. C60 is a better choice than ultra-small nanocrystals due to its monodispersion. Moreover, C60 provides accessible energy levels to prompt resonant tunneling through SiO2 at high fields. However, this process is quenched at low fields due to HOMO-LUMO gap and large charging energy of C60. Furthermore, we demonstrate an improvement of more than an order of magnitude in retention to program/erase time ratio for a metal nanocrystal memory. This shows promise of engineering tunnel dielectrics by integrating molecules in the future hybrid molecular-silicon electronics., Comment: to appear in Applied Physics Letters