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In this study, dual-gate thin-film transistors with low-temperature polysilicon as the active channel layer are thoroughly investigated. Under a large current operation where a high voltage is applied, impact ionization occurs near the drain, generating a large number of electron-hole pairs. Owing to the positive bias applied to the gate and drain, holes accumulate on the backside of the channel, which causes an earlier turn-on in the sub-channel, as is observed in the I-V characteristics of the saturation region. By enlarging the highly doped region between the double gates in the channel, the threshold voltage shift can be completely suppressed, and the leakage current rise can be reduced. The electric field simulation using Silvaco TCAD was consistent with the experimental results. Finally, a series transistor structure is used to measure the impact after the operation condition and further verify the physical model. [ABSTRACT FROM AUTHOR]

FinFETs and ultrathin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI (tBOX = 20 nm), and SOI FinFETs (t BOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the tBOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibit faster downscaling degradation than UTBB FDSOI probably due to the nature of multigate devices whose vertical electrical field should increase faster than planer devices during scaling. [ABSTRACT FROM PUBLISHER]

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed. [ABSTRACT FROM AUTHOR]

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed. [ABSTRACT FROM AUTHOR]

This paper describes the rectification responses exhibited by two kinds of SiGe HBTs when electromagnetic interference (EMI) is injected at the base of the transistor. The variation of the EMI induced DC offset after hot carrier stress is also studied. The experimental results show that the EMI response of a single SiGe HBT is different from that of a Si BJT. With interference present, the DC current gain increases at low base-emitter (BE) bias and decreases at larger V BE values. The absence of AC crowding induced DC crowding along with the base recombination current accounts for the increase of current gain. The base-width effect and the high-injection effect tend to decrease the gain in presence of interference. The simulation results show that the Gummel–Poon model is able to quantitatively model the EMI response of a SiGe HBT. [ABSTRACT FROM AUTHOR]

This paper reports the experimental investigation of hot carrier stress (HCS) and constant voltage stress (CVS) in high- $\kappa$ Si-based tunnel FETs. For the devices in this paper, due to the large injection of cold carriers and to the presence of traps in the gate dielectric, the degradation of the transfer characteristics under CVS is much more severe than under HCS. The experimental results show that the sub-threshold swing remains stable under both HCS and CVS conditions, and it is not influenced by the stress-induced increase of the interface trap density. [ABSTRACT FROM PUBLISHER]

In this work, the InAs/AlSb high electron mobility transistors (HEMTs) on GaAs semi-insulating substrate using refractory iridium (Ir) gate technology was proposed. The Ir-gate exhibited a superior metal work function which was beneficial for increasing Schottky barrier height of InAs/AlSb heterostructures to 0.58 eV. Compared to the Ti-gate HEMT, the Ir-gate HEMT shows higher threshold voltage and lower gate leakage current owing to its higher Schottky barrier height and higher melting point. Moreover, the Ir-gated HEMT also shows the manifest stability improvement of DC characteristics under hot carrier stress as the Ti and As diffusion is alleviated. [ABSTRACT FROM AUTHOR]

Damage of bipolar transistors (BJTs) during the mission could affect their response to electromagnetic interference (EMI) and change the Integrated Circuit (IC)’s electromagnetic susceptibility (EMS). This work investigated the effect of hot carrier stress on BJT’s response to EMI. The experimental results demonstrate that the base current increases under EMI and the amplitude enlarges after hot carrier stress. The variation of EMI induced collector current shift after hot carrier stress depends on the base supply resistance Rt. When Rt = 0, I C shift in presence of EMI is not affected by hot carrier stress whereas in the case of Rt ≠ 0, the EMI induced I C increment reduces or even reverses in variation direction. When the base terminal is biased by a current source, the voltage across the emitter-base junction drops more significantly after hot carrier stress. [ABSTRACT FROM AUTHOR]

The effects of oxygen ambiance on electrical characteristic degradation phenomena in a-InGaZnO thin film transistor with different biases and temperatures are investigated. It can be found that oxygen is substantially adsorbed on the backchannel and results in device instabilities during positive gate bias stress. However, visible light irradiation is found to desorb the adsorbed oxygen ions and this verifies that oxygen dominates the degradation behavior. Moreover, comparing with that in vacuum, hot-carrier stress in oxygen ambiance leads to an extra potential barrier height near the drain side due to oxygen adsorption and causes asymmetric degradation. Furthermore, the asymmetric degradation behavior after hot-carrier stress in oxygen ambiance is suppressed at high temperature due to temperature-induced oxygen desorption or heat-induced holes injecting into the gate insulator. [ABSTRACT FROM AUTHOR]

Over-voltage RF stress was applied to an LC dual-resonance injection-locked frequency divider (ILFD) to study the post-stress ILFD RF performance. The LC ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process and it was stressed at the supply voltage of 2.3 V for 5 h. The dual-resonance ILFD has dual-band locking ranges and it uses series-peaking injection MOSFET. The over-voltage RF stress reduces both the high-frequency and low-frequency band locking ranges. The ILFD current consumption can decrease or increase with stress time, and this depends upon the stress condition. The phase noise in the injection-locked state can decrease with stress time. [ABSTRACT FROM AUTHOR]

This letter studies the effects of hot carrier stress (HCS) in laterally diffused silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors. After HCS, threshold voltage and subthreshold swing degrade, while the ON-state current exhibits degradation after an abnormal spike due to hole trapping in the resist-protective oxide. Impact ionization simulation shows that low doping concentrations in the drift region cause a severe Kirk effect under HCS and more severe degradation at higher gate voltages. However, degradation in the channel contrasts with the simulation result, which suggests an additional mechanism. Variable temperature HCS confirms that channel degradation is instead dominated by temperature. [ABSTRACT FROM PUBLISHER]

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage ( V GS ) and high drain voltage ( V DS ), reduction of the ON-resistance ( R ON ) is observed. At stress times at which R ON almost reaches its constant level, an increase of the drain leakage in OFF state ( V DS = −60 V, V GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS. [ABSTRACT FROM AUTHOR]

This paper, for the first time, investigates hot carrier effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition. [ABSTRACT FROM AUTHOR]

Since it is generally accepted that interface states play an important role in MOS device degradation, measurement tools, like charge pumping (CP) gain more and more influence in interface characterization and reliability issues. In this paper, we point out that an often neglected and hardly published constant base-level technique offers more flexibility and more accuracy than a classical constant amplitude technique which provides the well-known Gaussian-like CP curve. We present both energetic and lateral sensitive profiling techniques and point out several sources of errors that can occur when CP experiments are executed. Two different energetic profiling techniques are compared by means of a case study on negative bias temperature instability. In order to determine the exact location of degradation inside the transistor channel, the seldom published but well working constant field channel modulation technique is introduced as a special feature of the constant base-level technique. The tested devices are PMOS transistors with a 30-nm SiO2 gate oxide and a gate length of 6 mum. [ABSTRACT FROM PUBLISHER]

High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices. [ABSTRACT FROM PUBLISHER]

Abstract: This paper is a report on the effect of a single perpendicular grain boundary on the hot-carrier and high current stability in high performance polycrystalline silicon (poly-Si) thin film transistors (TFTs). Under a hot carrier stress condition (Vg=Vth+1 V, Vd=12 V), the poly-Si TFT with a single grain boundary is superior to the poly-Si without any grain boundary because of the smaller free carriers available for electric conduction. The shift of transconductance in poly-Si TFT with a single grain boundary is less than 5% after hot carrier stress during a period of 1000 s. The shift of transconductance is about 25% in the case of the poly-Si TFTs without a grain boundary in the channel. On high current stress, the poly-Si TFT without the grain boundary is less degraded than the poly-Si TFT with the grain boundary because the concentrated electric field near the drain junction is lower. [Copyright &y& Elsevier]

Abstract: Low specific on-resistance, high packing densities, and large blocking voltage capabilities have all made U-shaped trench-gated metal-oxide–Si field-effect transistor (UMOSFET) the leading candidate in power electronic applications. However, hot carrier and Fowler Nordheim stresses are major reliability concerns for UMOSFETs. In studying the effects of these stresses on device lifetime, charge pumping (CP) has proven to be a versatile transistor characterization technique. For its application “conventional” CP, however, needs four terminal transistors and features the substrate current as its main output. Often a UMOSFET has only three terminals and no substrate contact is included in the device. We report on an adaptation of the CP technique, which renders it applicable on three-terminal UMOSFETs and other three-terminal transistors. The three-terminal CP is applied to n-channel UMOSFETs, and is used to evaluate the effects of electrical stresses applied to the UMOSFETs. [Copyright &y& Elsevier]

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-κ gate stack devices are severe than the one in the SiO2/poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress. [ABSTRACT FROM PUBLISHER]

Hot carrier and soft breakdown effects are evaluated experimentally. A methodology to systematically study hot carrier and soft breakdown effects on RF circuits is developed. Device stress measurement and SpectreRF simulation are conducted to evaluate the impact of hot carrier and soft breakdown effects on RF circuits such as low-noise amplifier and voltage-controlled oscillator performances. Two design techniques to build reliable RF circuits are proposed. [ABSTRACT FROM PUBLISHER]

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/Lnpn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on It2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device [ABSTRACT FROM PUBLISHER]

This letter investigates the abnormal off-current behavior induced by hot carrier stress (HCS) in p-channel double diffused drain metal-oxide-semiconductor transistors with a shallow trench isolation (STI) structure. According to ISE-TCAD simulation, the electric field at the drain-side corners of the high-voltage n-well (HVNW) adjacent to the STI trench is stronger than the electric field in the channel center in width direction. Moreover, because a nitride layer acts as a buffer in STI, the electrons generated by impact ionization at the corners of the HVNW can be easily trapped in the nitride layer or at the liner oxide/nitride layer interface. Furthermore, the extension of electron trapping in STI from drain to source during HCS forms the off-current conductive path. Based on the charge pumping measurements at different operation conditions, this path formation is further demonstrated by the comparisons of charge pumping measurements between initial state and after HCS. [ABSTRACT FROM AUTHOR]

Abstract: Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case. [Copyright &y& Elsevier]

In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of Imin is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low VTH ∼ 1.32 V, excellent subthreshold swing ∼0.141 V/dec, and high ION/Imin current ratio ∼1.98 x 107. [ABSTRACT FROM AUTHOR]