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Two-dimensional transient analyses of GaNMESFETs are performed in which a three level compensation model is adopted for a semi-insulating bufferlayer, where a shallow donor, a deep donor and adeepacceptorare included. Quasi-pulsedI-V curves are derivedfromthe transient characteristics. It is shown that so called current collapse or current reduction is more pronounced foracase with higher acceptor density in the buffer layer,because trapping effects become more significant. It is also shown that the current reduction is more pronounced when the drain voltage is lowered from a higher drain bias during turn-on.

Two-dimensional transient simulation of a GaN MESFET is performed in which deep levels in a semiinsulating buffer layer is considered. It is shown that the drain voltage VD is raised, the drain current overshoot the steady-state value, and when VD is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.

Two-dimensional transient simulation of GaAs FETs are performed in which substrate traps, surface states and impact ionization of carriers are considered. The mechanisms of lag phenomena and so-called power compression are discussed. It is shown that the drain-lag occurs mainly due to substrate traps, and the gate-lag mainly by surface states. Obtained quasi-pulsed I-V curves clearly indicate that the power compression can occur both due to substrate traps and due to surface states. Effects of the impact ionization on these phenomena are also discussed.

Effects of surface states on breakdown and gate-lag phenomena in narrowly-recessed-gate GaAs MESFETs are studied by two-dimensional (2-D) analysis. It is shown that the breakdown voltage could be raised when moderate densities of surface states are included. However, in a case with relatively high densities of surface states, the breakdown voltage could be drastically lowered when introducing a narrowly-recessed-gate structure. It is suggested that there is a trade-off relationship between raising the breakdown voltage and reducing the gate-lag.