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IntroductionMango is a vital horticultural fruit crop, and breeding is an essential strategy to enhance ongoing sustainability. Knowledge regarding population structure and genetic diversity in mango germplasm is essential for crop improvement.MethodsA set of 284 mango accessions from different regions of the world were subjected to high-throughput sequencing and specific-locus amplified fragment (SLAF) library construction to generate genomic single-nucleotide polymorphism (SNP).ResultsAfter filtering, raw data containing 539.61 M reads were obtained. A total of 505,300 SLAFs were detected, of which, 205,299 were polymorphic. Finally, 29,136 SNPs were employed to dissect the population structure, genetic relationships, and genetic diversity. The 284 mango accessions were divided into two major groups: one group consisted mainly of mango accessions from Australia, the United States, Cuba, India, Caribbean, Israel, Pakistan, Guinea, Burma, China, and Sri Lanka, which belonged to the Indian type (P1); the other group contained mango accessions from the Philippines, Thailand, Indonesia, Vietnam, Cambodia, Malaysia, and Singapore, which belonged to Southeast Asian type (P2). Genetic diversity, principal component analysis (PCA), and population structure analyses revealed distinct accession clusters. Current results indicated that the proposed hybridization occurred widely between P1 and P2.DiscussionMost of the accessions (80.99%) were of mixed ancestry, perhaps including multiple hybridization events and regional selection, which merits further investigation.

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 × 10-3. Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8× with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.

Convolutional Neural Networks (CNNs) are effective and mature in the field of classification, while Spiking Neural Networks (SNNs) are energy-saving for their sparsity of data flow and event-driven working mechanism. Previous work demonstrated that CNNs can be converted into equivalent Spiking Convolutional Neural Networks (SCNNs) without obvious accuracy loss, including different functional layers such as Convolutional (Conv), Fully Connected (FC), Avg-pooling, Max-pooling, and Batch-Normalization (BN) layers. To reduce inference-latency, existing researches mainly concentrated on the normalization of weights to increase the firing rate of neurons. There are also some approaches during training phase or altering the network architecture. However, little attention has been paid on the end of inference phase. From this new perspective, this paper presents 4 stopping criterions as low-cost plug-ins to reduce the inference-latency of SCNNs. The proposed methods are validated using MATLAB and PyTorch platforms with Spiking-AlexNet for CIFAR-10 dataset and Spiking-LeNet-5 for MNIST dataset. Simulation results reveal that, compared to the state-of-the-art methods, the proposed method can shorten the average inference-latency of Spiking-AlexNet from 892 to 267 time steps (almost 3.34 times faster) with the accuracy decline from 87.95 to 87.72%. With our methods, 4 types of Spiking-LeNet-5 only need 24–70 time steps per image with the accuracy decline not more than 0.1%, while models without our methods require 52–138 time steps, almost 1.92 to 3.21 times slower than us.

Vertical Hall sensors (VHSs), compatible with complementary metal oxide semiconductor (CMOS) technology, are used to detect magnetic fields in the plane of the sensor. In previous studies, their performance was limited by a large offset. This paper reports on a novel CMOS seven-contact VHS (7CVHS), which is formed by adding two additional contacts to a traditional five-contact VHS (5CVHS) to alleviate the offset. The offset voltage and offset magnetic field of the 7CVHS are reduced by 90.20% and 88.31% of those of the 5CVHS, respectively, with a 16.16% current-related sensitivity loss. Moreover, the size and positions of the contacts are optimized in standard GLOBALFOUNDRIES 0.18 μm BCDliteTM technology by scanning parameters using FEM simulations. The simulation data are analyzed in groups to study the influence of the size and contact positions on the current-related sensitivity, offset voltage, and offset magnetic field.

Aiming at the practical constraints of high resource occupancy and complex calculations in the existing Spike Neural Network (SNN) image classification model, in order to seek a more lightweight and efficient machine vision solution, this paper proposes an adaptive threshold Spike Neural Network (SNN) model of lateral inhibition of Spike-Timing-Dependent Plasticity (STDP). The conversion from grayscale image to pulse sequence is completed by convolution normalization and first pulse time coding. The network self-classification is realized by combining the classical Spike-Timing-Dependent Plasticity algorithm (STDP) and lateral suppression algorithm. The occurrence of overfitting is effectively suppressed by introducing an adaptive threshold. The experimental results on the MNIST data set show that compared with the traditional SNN classification model, the complexity of the weight update algorithm is reduced from O(n2) to O(1), and the accuracy rate can still remain stable at about 96%. The provided model is conducive to the migration of software algorithms to the bottom layer of the hardware platform, and can provide a reference for the realization of edge computing solutions for small intelligent hardware terminals with high efficiency and low power consumption.

This paper studies the effects of the covering layers on the performance of a cross-like Hall plate. Three different structures of a cross-like Hall plate in various sizes are designed and analyzed. The Hall plate sensitivity and offset are characterized using a self-built measurement system. The effect of the P-type region over the active area on the current-related sensitivity is studied for different Hall plate designs. In addition, the correlation between the P-type covering layer and offset is analyzed. The best structure out of three designs is determined. Besides, a modified eight-resistor circuit model for the Hall plate is presented with improved accuracy by taking the offset into account.

In this paper, a new single-device three-dimensional (3D) Hall sensor called a cross-shaped 3D Hall device is designed based on the five-contact vertical Hall device. Some of the device parameters are based on 0.18 μm BCDliteTM technology provided by GLOBALFOUNDRIES. Two-dimensional (2D) and 3D finite element models implemented in COMSOL are applied to understand the device behavior under a constant magnetic field. Besides this, the influence of the sensing contacts, active region’s depth, and P-type layers are taken into account by analyzing the distribution of the voltage along the top edge and the current density inside the devices. Due to the short-circuiting effect, the sensing contacts lead to degradation in sensitivities. The P-type layers and a deeper active region in turn are responsible for the improvement of sensitivities. To distinguish the P-type layer from the active region which plays the dominant role in reducing the short-circuiting effect, the current-related sensitivity of the top edge (Stop) is defined. It is found that the short-circuiting effect fades as the depth of the active region grows. Despite the P-type layers, the behavior changes a little. When the depth of the active region is 7 μm and the thickness of the P-type layers is 3 μm, the sensitivities in the x, y, and z directions can reach 91.70 V/AT, 92.36 V/AT, and 87.10 V/AT, respectively.

This work studies the effects of an aluminum covering on the performance of cross-like Hall devices. Four different Hall sensor structures of various sizes were designed and fabricated. The sensitivity and offset of the Hall sensors, two key points impacting their performance, were characterized using a self-built measurement system. The work analyzes the influences of the aluminum covering on those two aspects of the performance. The aluminum layer covering mainly leads to an eddy-current effect in an unstable magnetic field and an additional depletion region above the active region. Those two points have influences on the sensitivity and the offset voltage, respectively. The analysis guides the designer whether to choose covering with an aluminum layer the active region of the Hall sensor as a method to reduce the flicker noise and to improve the stability of the Hall sensor. Because Hall devices, as a reference element, always suffer from a large dispersion, improving their stability is a crucial issue.