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In this work, the suppression of hydrogen diffusion in top-gate InGaZnO thin film transistors (TFTs) was observed. Under positive-bias temperature stress, the threshold voltage in short-channel devices was negatively shifted; this shift was attributed to hydrogen diffusion. To inhibit hydrogen migration, low-temperature high-pressure (LTHP) fluorine treatment was subsequently utilized. Under supercritical fluid states, fluorine, the most electronegative species of all elements, acted as a reactant and reduced mobile hydrogen. It was confirmed that the treatment benefited the characteristic properties of InGaZnO TFTs with varied channel lengths, especially in devices with short channels. The reliability of devices under stress improved through the LTHP treatment; the effects of suppression of hydrogen diffusion were illustrated by the energy band and capacitance–voltage curves of devices. Energy-dispersive X-ray spectroscopy of the specimen treated with LTHP indicated the presence of fluorine, which ensured the contribution of the treatment. Thus, LTHP treatment enables the realization of small-sized high-performance top-gate InGaZnO TFTs.

In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ( $\text{I}_{\mathrm{ on}}$ ) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device.

This letter investigates degradation during alternating current (AC) operations in low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) produced using the selective excimer laser annealing (ELA). Different degrees of degradation, on-current increase and threshold voltage (Vth) shift were observed after AC operation stress in three devices with different ELA energies. Although a higher ELA energy device has a higher on-current, this will lead to higher protrusion and a stronger electrical field in the active layer. This stronger electrical field will cause serious electron trapping in the grain boundary trap (Ntrap), leading to more serious degradation than that found in the lower ELA energy devices. Finally, COMSOL simulations and C-V measurements were executed to verify the physical mechanism.

This work studies the effect of the location of the light shielding (LS) layer on negative bias illumination stress (NBIS) instability in self-aligned top-gate amorphous indium-gallium-zinc oxide thin-film transistors (SA-TG a-InGaZnO TFTs). Although the NBIS instability can be mitigated by introducing a fully covered LS layer, it causes an unwanted parasitic capacitance, as evidenced by capacitance–voltage ( ${C}$ – ${V}$ ) measurements. An alternative solution, in which the device that is partially covered by the LS layer at the source side, is proposed to optimize the tradeoff. This study suggests that an LS layer could be adopted in the SA-TG configuration, as it is versatile in different structural designs, depending on the requirement of targeted applications.

In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (ION) increase, and an off-current (IOFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels.

This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.

High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.

This paper demonstrates the cumulative effects of compressive stress and high current stress at high temperature in flexible a-InGaZnO4 thin-film transistors. An abnormal hump can be found in the subthreshold regime in the results from a reliability test that combines high temperature and high current stress with mechanical bending at 10 mm. During this stress, holes will tend to inject into the defects in the etching stop layer near the source side, which is induced by compressive bending. A COMSOL simulation was performed and confirmed that defect generation occurs in the etching stop layer during compressive bending. Further, the path of the back-channel leakage current caused by the localized trapped holes was also confirmed by changing the width/length of thin film transistors (TFTs) in the reliability test. The precise hole trapping distribution was verified by a single side capacitance-voltage measurement and source/drain interchange measurement.

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.

In this work, degradation due to carrier injection at the etch-stop layer was observed under dynamic switching. A significant threshold voltage shift is observed in alternating current stress but is absent in direct current stress. A model which transitions from the accumulation to depletion phases indicates electron-trapping at the etch-stop layer since the transition time is insufficient for carriers to drift back to the source/drain electrodes. Results are discussed through both horizontal and lateral band diagrams to confirm back channel injections. Also, comparing transfer curves with capacitance-voltage curves at the same threshold voltage in different structure devices provides direct evidence of electron-trapping regions. Finally, COMSOL simulation is performed to confirm the difference in electron-trapping between back channel and corner regions, a difference which leads to an abnormal hump during capacitance-voltage measurements.

Degradation in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (S.S.) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in S.S. values which appears in hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.