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The addition of Ag to Cu-Ga-In precursors for synthesizing (Ag,Cu)(In,Ga)Se2 (ACIGS) thin films has shown benefits including improved adhesion, greater process tolerance, and potential for improved device performance. In this study, reaction pathways to form Cu(In,Ga)Se2 (CIGS) and ACIGS were studied by time-progressive reactions at 450 °C in a 5% Ar/H2Se atmosphere followed by ex situ characterization. Results indicated that the addition of 25% Ag/(Ag+Cu) to the CIGS film reduces the reaction time by 50%. X-ray diffraction (XRD) analysis of CIGS films showed that the CuInSe2 phase initially formed after 3.5 min. The slow reaction of the stable γ-Cu9(In,Ga)4 phase, however, required more than 20 min to complete. Importantly, the addition of Ag to the CIGS film accelerated the reaction. Energy-dispersive X-ray spectroscopy shows that Ga/(Ga+In) grading occurs in the first 10 min of the reaction. XRD analysis showed that the chalcopyrite phase fully forms after 10 min and no significant changes were observed in samples selenized from 10–45 min. Reaction pathways of Ag-alloyed films were further characterized using in situ high temperature XRD analysis. The onset temperature of Se reaction was detected at 230 °C and a AgIn2 phase transformation to (Ag,Cu)In2 occurred during the early stage of the reaction.

The substitution of Ag for Cu in Cu(Ga, In)Se 2 has been shown to optimize the bandgap of the chalcopyrite while decreasing defect density and formation temperature. The synthesis of chalcopyrite via selenization of metal precursor films with a complete substitution of Ag for Cu was studied both in-situ during selenization using high temperature x-ray diffraction and ex-situ using electron microcopy. AgInSe 2 formation at low temperatures was limited by the availability of Ag in the liquid phase resulting in the formation of Ag-deficient Ag-In-Se phases. Ga alloying into AgInSe 2 at high temperature was limited by the stability of (Ga, In) 2 Se 3 .

Co-evaporation of Cu-KF-In-Se was performed on substrates with varied surface Na compositions. Compositions of interest for photovoltaic absorbers were studied, with ratios of (K+Cu)/In ~ 0.85 and K/(K+Cu) ~ 0 - 0.57. Soda-lime glass (SLG) substrates led to the most Na by secondary ion mass spectrometry, while SLG/Mo and SLG/SiO2/Mo substrates led to 3x and 3,000x less Na in the growing film, respectively. Increased Na content favored Cu1-xKxInSe2 (CKIS) alloy formation by X-ray diffraction (XRD), while decreased Na favored the formation of CuInSe2 + KInSe2 mixed-phase films. Scanning electron microscopy and energy dispersive X-ray spectroscopy revealed the KInSe2 precipitates to be readily recognizable planar crystals. Extrinsic KF addition also drove diffusion of Na out from the various substrates and into the growing film, in agreement with previous reports. Time-resolved photoluminescence showed enhanced minority carrier lifetimes for films with moderate K compositions (0.04 < K/(K+Cu) < 0.14) grown on Mo. Due to the relatively high detection limit of KInSe2 by XRD and the low magnitude of chalcopyrite lattice shift for CKIS alloys with these compositions, it is unclear if the lifetime gains were associated with CKIS alloying, minor KInSe2 content, or both. The identified Na-K interdependency can be used to engineer alkali metal bonding in Cu(In,Ga)(Se,S)2 absorbers to optimize both initial and long-term photovoltaic power generation.

Low-temperature (170°C) Cu/In wafer-level and chip-level bonding for good thermal budget has been successfully developed for 3-D integration applications. For the well-bonded interconnect, Cu2In and Cu7In3 phases with high melting temperature of 388.3°C and 632.2°C can be formed, indicating high thermal stability. In addition, stable low specific contact resistance of bonded interfaces can be achieved with the values of approximately 0.3×10-8 Ω-cm2. In addition to exceptional electrical characteristics, the results of electrical reliability assessments including current stressing, temperature cycling, and unbiased HAST show excellent stability of Cu/In bonds without obvious deterioration. The low-temperature Cu/In bonding technology presents good bond quality and electrical performance, and possesses a great potential for future applications of 3-D interconnects.

Flip-chip chip-scale packaging (FCCSP) has recently emerged as a package solution achieving superior performance over traditional wire-bonding technology. There are also further possible advances for the assembly process such as under-fill and molding to be more cost effective. We propose an innovative process of a heterogeneous integration of the organic substrate and the standard FCCSP assembly process. This is achieved with technical and material improvements; the result is a new type of molding and under-fill technology that has higher process efficiency than conventional molding and under-fill and demonstrates good thermal dissipation and warpage control. The new process and the resulting package reliability are validated by test vehicle engineering verifications. This ‘laminated’ FCCSP platform is a type of ‘chip-last embedded die’ structure that is extendable to support stackable packages for use in advanced package-on-package applications.

Three-dimensional (3D) integration method has become the candidate to extend the Moore's law due to its heterogeneous integration, multiple functionality, and low power consumption. To realize 3D integration, Through-silicon via (TSV) has emerged as a good approach to provide higher wiring density, shorter interconnect, and simpler structure. In this study, the overall processes of TSV including via etching, liner deposition, and copper filling are investigated. First of all, in the etching process, the mechanism and the solution of micro-masking effect were studied. Secondly, in the liner deposition, the analysis of different TSV liners was done by using its step coverage, stress, breakdown voltage, and leakage. Finally, in the process of the copper filling, a novel sealing bump method was proposed because of its advantages in less process steps and the self-formation of bonding pad. Test vehicles, including daisy chain, Kelvin structure, and comb structure, were designed with various sizes of TSV to verify the quality by using electrical measurements. In addition, the design rules of TSV were also investigated with reliability tests on different arrangement and pitch of TSV. This study not only proposes a novel design and structure of sealing bumping TSV method, but also summarizes the integration of this TSV with its excellent electrical property and reliability performance, providing a promising technique for TSV integration in 3D IC. Furthermore, the investigation results of design rules provide a useful guideline of TSV placement in the IC layout for future 3D integration.

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.

Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.

Single-walled aluminosilicate nanotubes are attractive materials for construction of nanofluidic devices. They have a well-defined structure, a hydrophilic interior with periodic wide and narrow regions, precisely tunable length and diameter, and a functionalizable interior for tuning mass transport and adsorption properties. We report a computational and experimental investigation that highlights the unique adsorption and diffusive water transport properties of these nanotubes. Axial self-diffusivities of water molecules (at loadings ranging from near-infinite dilution to near-saturation) are calculated by molecular dynamics (MD) simulations, whereas adsorption properties are computed with grand canonical Monte Carlo (GCMC) simulations and are also compared to experimental data. The transport diffusivities are evaluated through the Darken approximation. Water transport in these nanotubes at room temperature was observed to occur via Fickian diffusion. The self-diffusivity decreases with an increase in wa...

We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 μm CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5 × 5 mm(2) in area, with 16 channels of 150 μm-in-length neural probe array on the back-side, 200 μm-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5 × 6 probe array, 3 × 14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 μW power consumption, 108 dB CMRR and 2.56 μVrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.

Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with $\mu$ -probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of $\mu$ -probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 $\times$ 24 $\mu$ -probe array with embedded TSVs is fabricated on a $5\times 5\ {\rm mm}^{2}$ chip and bonded on the back side of the interposer. Thus, each channel contains 6 $\times$ 6 $\mu$ -probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus ( $\mu$ -SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 $\mu{\rm W}$ for 16-channel neural sensing.

A novel CMOS-compatible bond structure using Cu-to-Cu bonding with Ti passivation is demonstrated at low temperature and investigated. With the Ti protection of inner Cu, Cu bonding temperature can be reduced to 180 °C. In addition, excellent electrical stability against humidity and temperature cycling is achieved. Diffusion behavior and mechanism of Cu and Ti are also discussed. With excellent bond results and reliability, this bonded scheme has the potential to be applied in 3-D integration.

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, an energy-efficient configurable lifting-based discrete wavelet transform (DWT) is proposed for a high-density neural sensing microsystems to extract the features of neural signals by filtering the signals into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted via the configurable datapth. Moreover, the power-gating and clock-gating techniques are utilized to further reduce the energy consumption for the energy-limited bio-systems. The proposed configurable DWT is designed and implemented using TSMC 65nm CMOS low power process with total area of 0.11 mm 2 and power consumption of 26 μW. Moreover, this proposed DWT is also implemented in Lattice MachXO2-1200 FPGA and integrated in a 2.5D heterogeneously integrated high-density neural-sensing microsystem with the power consumption of 211.2 μW.

Bio-signal probes that provide stable observation with high-quality signals are crucial for understanding how the brain works and how the neural signal transmits. Because bio-signals are weak and noisy, the length of the string connecting the sensor and Complementary Metal-Oxide-Semiconductor (CMOS) circuit significantly impacts biosignal quality. The collected weak signals from the sensor must pass through a series of interconnections and interfaces that introduce noise and lead to bulky packaged systems. This work uses through-silicon via (TSV) technology to connect the μ-probe array bio-sensor and CMOS circuit located on opposite sides of a chip for brain neural sensing applications. With the elimination of wire bonding and the reduction of the soldering, bio-signal quality can be significantly improved.

In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input G m -stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18μm CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67μW for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826μV rms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.

Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.

Three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, are investigated for the application of 3D interconnects. Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 °C. In addition, for Cu/Ti-Ti/Cu bonding, Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This method can further decrease bonding temperature. All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.

In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18μm CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6μW power consumption and 0.032-mm2 area. The FoM of this ADC is 49.4fJ/conversion-step.

Reaction pathways were followed for selenization of CuGa/In precursor structures using in-situ high temperature X-ray diffraction (HTXRD). Precursor films were deposited on Na-free and Na-doped Mo (3 and 5 at %)/Na-free glass. The precursor film was constituted with CuIn, In, Cu9Ga4, Cu3Ga, Cu16In9 and Mo. HTXRD measurements during temperature ramp selenization showed CIS formation occurs first, followed by CGS formation, and then mixing on the group III sub-lattice to form CIGS. CIGS formation was observed to be complete at ~450 °C for samples deposited on 5 at % Na-doped Mo substrates. MoSe2 formation was evidenced after the CIGS synthesis reaction was complete. The Ga distribution in the annealed CIGS was determined by Rietveld refinement. Isothermal reaction studies were conducted for CIGS (112) formation in the temperature range 260-320 °C to estimate the rate constants.

A low temperature bonding technology of Sn/In composite solder bonded to Cu interconnect is proposed and investigated. The intermetallic compounds formed in the bonded interconnects can survive well in the following process. The Sn/In-Cu interconnects bonded at low temperature all exhibit excellent electrical performance and high resistance to multiple current stressing, showing a great potential in 3D applications.

In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.

In this paper, mechanical bonding behaviors of micro-bumps in 2.5D/3D ICs assembly are studied theoretically. Solder force and spring constant of micro-bumps with different bond pad structures are estimated by using Surface Evolver. Deformations of dies with corresponding flattening distances are evaluated based on flexural theory and three-dimensional contact theories. Allowable coplanarity of bond surface or die warpage during both mass reflow and thermal compression bond is developed. Guidelines to ensure successful bond and corresponding structural designs are earned.

Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has six temperature sensitive ring oscillators (TSROs) generating frequency proportional to temperature. It dynamically selects the proper TSRO to convert the frequency into digital readings according to voltage status provided by PV sensors. With known process and voltage information from PV sensors, a pure temperature measurement result can be obtained. The proposed PVT sensors are designed in TSMC 65nm CMOS technology. This work can be dynamically operated over an ultra-low voltage range from 0.25V to 0.5V. Only 2.3μW is consumed at 0.25V. They can achieve 0.15 C resolution and 50k samples/sec conversion rate.

This paper presents a Through-Silicon-Via (TSV) based double-side integrated microsystem for brain neural sensing applications. Figure 6.3.1 shows the structure of the double-side integrated microsystem. MEMS neural microprobe array and low-power CMOS readout circuit are fabricated on two sides of the same silicon substrate, and TSV's are used to form a low impedance interconnection between the microprobe and CMOS circuitry, thus providing the shortest signal transmission distance from sensors to circuits. The low parasitic impedance of TSV minimizes transmission loss and noise. The overall chip is 5x5mm2, 350μm in thickness including 150μm probe height and 200μm TSV height, respectively. A total of 480 microprobes is divided into 4x4 sensing areas, forming 16channels. 16 TSV arrays are used to connect the microprobe outputs to 16 readout circuits fabricated on the opposite side of the silicon substrate. The proposed structure allows stacking of other CMOS chips onto the circuit side by TSV 3D IC technique.

A method of pressure sintering multilayer glass ceramic packages (MLC) that results in a hermetic product is described. Use of this process results in a reduced process time, and is achieved without the use of a die, which is commonly employed during pressure sintering. Complex glass ceramic multichip substrates have been sintered this way to produce products with a flat edge contour and minimal distortion of the internal vias. In this article, we present a model that provides the fundamental basis for the pressure sintering approach to processing MLC. In this semi-quantitative model, the mechanism of pressure sintering, i.e., the process of dimensional changes, is controlled by viscous flow induced by sintering, and lamination flow created by an applied pressure. The pressure sintering model is capable of predicting the flow, density, and dimensional changes of a glass ceramic carrier during pressure sintering in the absence of a die. Both the temperature and pressure schedules are time dependent, and the pressure can vary over a range from zero, corresponding to free sintering, to large pressures (up to at least 800 psi) that closely simulate experimental data.

Spurred by the advent of low-cost, high-speed complementary metal-oxide semiconductor (CMOS) devices, the ever-increasing demand for faster, smaller and cheaper systems, and global competitive pressures, many fundamental changes are taking place in the microelectronics packaging industry to better prepare it to meet the challenges of the next millennium for systems ranging from consumer electronics to large systems such as mainframes. With CMOS performance approaching emitter-coupled logic (ECL), CMOS is emerging as the engine of systems that span the entire spectrum of the microelectronics industry, fading the demarkation lines between systems of different form factors, and encroaching on the territory of ECL-based mainframes. Partly due to the insatiable desire of society for lower-cost systems with high performance, the recent past has witnessed a shrinking large-system market and migration toward small systems, as reflected by the widespread use of CMOS-based personal systems and portables today. Also evident is the convergence of computers, radios, phones and videos into one low-cost portable multimedia system possessing eventually all the functions of these equipment to more fully exploit the senses of mankind. Moreover, much attention is being given to thermal/power management and development of low-power submicron CMOS chips even for small systems such as personal computers in response to the rising power dissipation associated with high-speed CMOS integrated circuits, and the demand for more energy-efficient and environmentally correct systems. To tackle these changes mandating high speed, low cost, portability and low power dissipation, packaging needs to take on an evolutionary track for cost-effective solutions based on a plethora of package options in existence today, particularly in the areas of enabling technologies such as high-input/output (I/O) connectors (e.g., flip chip, tape automated bonding, ball grid arrays and flexible edge connectors), multichip module (MCM) packaging (involving, for example, organic cards and both ceramic and silicon-on-silicon MCMs), high-wiring-capacity organic laminates, as well as efficient heat-sinking. This article reviews the present and the future of these enabling packaging technologies, all favoring a high level of package integration, maximizing the benefits of integrated circuit (IC) performance gains through reducing packaging delays, and small package form factors.

In this study, measurements are made to validate the electrical performance of a Through Silicon Via (TSV) interconnection up to 40GHz, and the results of the wideband scalable model of TSV is proposed and compared with the measured data. Measurement of the TSV structure demonstrates its advantages of low parasitic capacitance and low insertion loss at high frequency.

In this paper, a detailed examination on TSV and cavity inductive coupled plasma (ICP) etching is presented. We investigated the relation such as etching loop number, TSV etching depth and etching rate. Due to particles knocked off from the hard mask and then fallen down to the TSV and cavity bottom, micro-masking issue becomes serious after ICP etching. In addition, parameters of isotropic etching, pressure, and RF bias were studied to investigate the process of micro-masking removal.

Bosch reactive ion etching is widely used for TSV formation. The micro-masking formed during etching can be successfully removed by adjusting the internal parameters during etching. The smooth high-aspect-ratio TSVs were further developed in wafer-level fabrication. Finally, a two-step etching process was developed to achieve tapered TSVs for the following Cu plating process.

In TSV 3D integration, stacking multiple dies would face a severe challenge of the thermal stress and V t scatter. In this paper, a fully on-chip self-calibrated process-temperature (PT) sensor is proposed to monitor the transistor variations (V tn , V tp ) and temperature of the intra-die for 3D-ICs. The process information and temperature can be decoupled using the process-sensitive and temperature-dependent ring oscillators. Based on TSMC 65nm CMOS process, this sensor achieves 367.5 pJ per conversion, and the sensitivities of V tn , V tp and the inaccuracy of temperature are merely ±1.6mV, ±0.8mV, and ±1.5oC, respectively.

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC packaging solution. As the 2.5D interposer design pushing towards smaller & shorter via due to I/O density and electrical performance, the warpage of thinner interposer is therefore much more challenging in thin wafer handling and assembly process. In this presentation, a TSV structure is introduced with fabricated interposer prototype, and could be assembled together with single-die/multi-chip on a substrate. The demonstrated interposer assembled in FCBGA (Flip Chip Ball Grid Array) has covered features such as low temperature fabrication process, low warpage, and low leakage with minimized TSV parasitic parameters. Electrical and stress characterizations, current density characterization up to 1100mA and Shadow Moire are performed and compared with simulation models for correlation study. Known-Good TSV and Si interposer are also reviewed and discussed in this presentation. Full validated reliability test, both die and package level, in conjunction with board level drop test, are presented to verify interposer fabrication, assembly process optimization, and interconnection stability.

The fabrication, detailed characterization, and molecular transport properties of nanocomposite membranes containing high fractions (up to 40 vol %) of individually-dispersed aluminosilicate single-walled nanotubes (SWNTs) in poly(vinyl alcohol) (PVA), are reported. The microstructure, SWNT dispersion, SWNT dimensions, and intertubular distances within the composite membranes are characterized by scanning and transmission electron microscopy (SEM and TEM), energy-dispersive spectroscopy (EDS), X-ray diffraction (XRD), XRD rocking curve analysis, small-angle X-ray scattering (SAXS), and solid-state NMR. PVA/SWNT nanocomposite membranes prepared from SWNT gels allow uniform dispersion of individual SWNTs in the PVA matrix with a random distribution of orientations. SAXS analysis reveals the length (∼500 nm) and outer diameter (~2.2 nm) of the dispersed SWNTs. Electron microscopy indicates good adhesion between the SWNTs and the PVA matrix without the occurrence of defects such as voids and pinholes. The transport properties of the PVA/SWNT membranes are investigated experimentally by ethanol/water mixture pervaporation measurements, computationally by grand canonical Monte Carlo and molecular dynamics, and by a macroscopic transport model for anisotropic permeation through nanotube-polymer composite membranes. The nanocomposite membranes substantially enhance the water throughput with increasing SWNT volume fraction, which leads to a moderate reduction of the water/ethanol selectivity. The model is parameterized purely from molecular simulation data with no fitted parameters, and shows reasonably good agreement with the experimental water permeability data.

Today, as global environmental regulations are being tightened, both IC and package technologies are also becoming far more complicated. More Moore and more than Moore, which manifest themselves in system-on-chip (SoC) and system-in-a-package (SiP), respectively, are being used more in combination to meet the ever-more-stringent cost and time-to-market requirements of consumer products with more functions built in them. In this presentation, I will review the challenges and opportunities to IC packaging as a direct outcome of the above trends to ensure SoC and SiP based IC packages meet the needs of the present generation without compromising the ability of future generations.

Solvent transport in multilayer thin film structures can induce damaging stresses. It is important to understand these quantitatively for the design of processing methods for microelectronics manufacture. As a model for such systems, this article focuses on the connection between solvent transport in a thin, supported film and the induced bending curvature of the film/substrate combination. We develop a simple mechanical model to calculate the bending curvature based on the transport-induced stresses. A phenomenological moving boundary description of non-Fickian solvent transport often found in glassy polymers has been used. The evaluation of dimensionless bending curvature for a number of generic cases is presented. As an application of the model, experimental data for a polymide (PI)/quartz-n-methyl-2-pyrrolidinone (NMP) system involving significant swelling (15–20%) of the PI film is analyzed. The analysis shows that the measured bending during the transport of NMP in the PI film compares well with that predicted based on an “intermediate,” non-Fickian diffusion mechanism of NMP, consistent with the finding obtained from a laser interferometric study. Estimation of the swelling-induced stress shows that it is large and as significant as that due to thermal “curing.”

WLCSP with Ni/Cu UBM and SnAgCu solder interconnect comply completely with European ROHS regulation. SnAgCu solder exhibits best solder joint thermal fatigue life in organic laminate BGA type package to organic PCB during gentle TCT condition, but whether means it can also work well in silicone die level package to organic PCB due to larger CTE mismatch during temperature cycling, is still necessary to be explored. In this report, the interfacial metallurgical reactions of solder joint of the combination of 0.3 mm SnAgCu solder ball and different melting point solder pastes such as Sn37Pb and Sn3.0Ag0.5Cu will be investigated in the wafer level CSP package with 0.5mm ball pitch. After appropriate SMT process at low, medium and high reflow temperature respectively on NSMD FR4 PCB with Cu-OSP surface finish, the sample is subject to TCT (-40-125/spl deg/C) 500 and 1000 cycle, then are followed by solder joint cross-section observation with SEM/EDX. The diverse failure mode on the metallurgical evolution in the interface and solder bulk itself is recorded to illustrate the solder joint integrity. The relationship among the fracture morphology and solder paste type is concluded as well. Furthermore, one new technology with polymer collar structure around the solder ball is integrated to discuss the whole SnAgCu solder joint integrity enhancement during the TCT test. A mature wafer level CSP with Sn37Pb solder ball will be used for comparison as well.