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We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage ( $\text{V}_{\textit {form}}$ ) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k $\Omega $ and demonstrate 4-bit programming at Rmax $=1\text{M}\Omega $ . Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

Phase Change Memory (PCM) materials can be damaged during plasma exposure leading to changes in phase transition behavior. Etch-induced damage and crystallization properties of GeSbTe (GST) were evaluated as a function of substrate temperature, plasma chemistry, and plasma exposure time. Enhanced damage formation is related to selective elemental depletion and non-volatilized etch residue retention in the near surface region. These experiments validate literature findings that crystallization time increases with reduction in film thickness for GST samples capped with a thin SiO2 film, indicating the presence of a modified layer which serves as an interface layer material. A direct comparison of passivating properties of hydrofluorocarbon and hydrocarbon on GST can be more conclusive with a fine tuning of film thickness and an evaluation of total residue retention with depth profiling.

Plasma etch residue formation and its removal from silicon nitride (SiN) films deposited at 200oC, 480oC and 700oC is explored. X-Ray Photoelectron Spectroscopy (XPS) measurements showed that SiN contains more nitrogen (N) and less oxygen (O) with increasing deposition temperature. SiN films were etched in an Inductively Coupled Plasma (ICP) reactor in a halogen/hydrofluorocarbon (H:HFC) gas mixture; the carbon (C) containing species in the resulting residue films were studied as a function of the H:HFC ratio in the plasma. Post-plasma etch cleaning methods of the SiN surface were compared, these included: wet treatment with diluted hydrofluoric acid (dHF), sputtering with argon (Ar) plasma, and combined dHF and Ar plasma. After etch, Secondary Ion Mass Spectroscopy (SIMS) and XPS data showed formation of fluorocarbon (FC) films on SiN. FC film thickness after etch was estimated from XPS to reach up to 2 nm. Ultimately the SiN etch rate was shown to drop with increasing deposited C thickness while the lower nitrogen content in the SiN film (i.e. 200oC) led to higher etch rate, which is in good agreement with literature. Ar plasma sputter turned out to be the most effective way of cleaning C residues: C surface content after Ar sputter was reduced to or below the reference data (unetched sample). In terms of wet treatment, an optimized chemistry was identified (AltChem) and post-RIE cleaning was more efficient than dHF in reducing C surface concentrations.

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles.

The scientific study of plasma discharges and their material interactions has been crucial to the development of semiconductor process engineering and, by extension, the entire microelectronics industry. In recent years, the proliferation of the big data business model has led to heightened interest in technology candidates with the potential to supplant CMOS architectures in critical metrics such as computational capacity or power consumption. These novel technologies share many common material elements with existing logic and memory devices, but the impact of mass fabrication techniques on their performance is largely unknown due to differences in the underlying physics of their operation. Two components are thus vital to this endeavor: fundamental evaluation of any emerging plasma process interactions and the ability to tailor any aspect of the plasma process necessary to produce the desired specifications. In this article, we review relevant advances in the study of plasma-induced damage mechanisms as well as characterization methods such as diagnostic probes and simulation tools. We also provide an outlook for the application of techniques such as plasma doping, area-selective etch/deposition, and heterogeneous integration. The frontiers of any new computing paradigms can only be explored through a focus on atomic scale engineering, and progress in the field of plasma science supplies the necessary toolset.

The Naval Research Laboratory (NRL) has developed a processing system based on an electron beam-generated plasma, where unlike conventional discharges produced by electric fields (DC, RF, microwave, etc.), ionization is driven by a high-energy (~ keV) electron beam. The resulting plasmas are characterized by large electron densities (10 10 –10 11 cm − 3 ) and low electron temperatures (0.3–1.0 eV). Accordingly, a large flux of ions can be delivered to substrate surfaces with kinetic energies of only a few eV, a feature that can be attractive to processing applications that require low damage and atomic layer precision. This work describes the salient features of these plasmas produced in mixtures of argon and sulfur hexafluoride (SF 6 ) and their use in silicon nitride etching, with particular attention paid to developing processing parameters relevant to atomic layer processing.

We demonstrate a CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing. The device demonstrates symmetric and linear conductance update, large on/off ratio and good retention while also withstanding high temperature treatments necessary for BEOL compatibility. Resistive switching in MO-ECRAM is observed with voltage pulses down to 10 ns and scales exponentially with voltage pulse amplitude, enabling parallel array operations without any selector/access devices. For the first time, we experimentally demonstrate fundamental techniques for fully- parallel array operations, stochastic update scheme and zero-shifting technique, and show a successful stochastic gradient descent algorithm demonstration in hardware using a MO- ECRAM array.

A baseline TiAl-containing ALD electrode is established, with properties in line with reported workfunction (WF) materials for scaled RMG nFETs, values below 4.6eV requiring a 25A layer. Furthermore, a novel ALD metal-compound material, MX, is shown to enable at least 10A further scaling of the electrode stack due to its superior scavenging power. It can be finely tuned by the film thickness, allowing for a remarkable 20-30meV WF delta per ALD cycle over a minimum 600meV range. The wet etchability of the electrodes makes multi-Vt and dual-WF integration possible. MX does not degrade transfer characteristics and reliability of RMG FinFETs, while the thinner nWF electrode enables reduced gate resistance, as verified down to 20nm metal gate lengths. For the first time, taking advantage of the MX compound scavenging power to control oxygen filaments, we demonstrate an all-ALD HfO 2 -based ReRAM. Forming voltages match those achieved by optimized PVD contacts, while scaling the active electrode thickness by a factor of 4x, down to 5nm. Conformality of the layers enables vertical-ReRAM architectures with reduced line resistance. We conclude the developed electrode can facilitate both logic scaling beyond the 10nm node, and 3D memory technology.

A reliability study for PCM and OTS intermixing was addressed. The buffer layer between PCM and OTS plays a key role in preventing PCM/OTS intermixing after BEOL processing thermal treatment. Besides cycling endurance, performance degradation due to interlayer intermixing was observed. Optimal device operation and an improved buffer layer allowed drastically improved cycling endurance from a few cycles to > 1E9 cycles.

In the ideal case, plasma-enhanced atomic layer etching enables the ability to not only remove one monolayer of material but also leave adjacent layers undamaged. This dual mandate requires fine control over the flux of species to ensure efficacy, while maintaining an often arduously low ion energy. Electron beam-generated plasmas are well-suited for etching at low ion energies as they are generally characterized by highly charged particle densities (1010–1011 cm−3) and low electron temperatures (

Over the course of the past few years, the semiconductor industry has continued to invent and innovate profoundly to adhere to Moore’s Law and Dennard scaling. At each of the technology nodes starting with 45nm, new materials and integration techniques, such as high-K & metal gates, double patterning techniques, and now 3D FinFet / Trigate device geometries are being introduced in order to maintain device performance. This places a large burden on unit process development to accommodate and deliver advanced process capability and is growing the need for the ultimate etch solution: etching with atomic layer precision. Atomic layer etching is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reactions, discrete reaction & activation steps, or extremely low ion energy etch plasmas are some of the pathways being pursued for precise sub-nanometer material removal. In this invited paper, previously published in SPIE, the ability to achieve atomic layer etch precision is reviewed in detail for a variety of material sets and implementation methods. For a cyclic approach most similar to a reverse ALD scheme, the process window to achieve a truly self-limited atomic layer etch process is identified and the limitations as a function of controlling the adsorption step, the irradiation energy, and the reaction process are examined. Alternative approaches, including processes to enable pseudo-ALE precision, are then introduced and results from their application investigated. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. Significant improvements however were obtained when applying PE-ALE approaches to small pitch patterns. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

Monitoring vacuum ultraviolet (UV/VUV) emission in plasma systems is challenging as it requires specialized diagnostic systems or sensors to be compatible with these devices. This study addresses different reactor configurations and plasma chemistries with various levels of UV emission and their effects on a known set of polymers. First, the effect of He plasma treatment of organic underlayer (NFC-1400) and e-beam resist (hydrogen silsesquioxane) on line-space patterning of polysilicon at sub-100 nm pitch was investigated. By applying He plasma exposure, both before and after patterning of the optical underlayer, a significant improvement in line edge roughness (LER) from 2.5 to 1.4 nm was observed. To understand the plasma treatment mechanisms, polymers were exposed to synchrotron VUV light at 62 nm (or 20.0 eV), which coincides with the He VUV emission range (50–60 nm), followed by etching of poly-Si, and were found to have similar LER results. The refraction index measurements for both the optical underlayer and the e-beam resist revealed the key finding that the polymers absorption maxima corresponded exactly to the wavelength of ∼60 nm. Second, the impact of inductively coupled and microwave plasma configurations on etch rates and chemical properties of photoresists were investigated. Identifying specific photon-induced modifications on polymers can help detect UV/VUV emission in the plasma and decouple ion and photon effects on materials. Poly(methyl methacrylate) and poly(4-vinylphenol)-based photoresists were exposed to argon (Ar) and nitrogen (N2) plasmas. Surface and elemental analyses confirmed that plasma effects on chemical modifications, surface roughness, and etch rate were significantly higher for poly(methyl methacrylate) compared to poly(4-vinylphenol)-based photoresists. Detailed elemental and molecular structure analyses of these polymers showed relatively higher damage to both species caused from the inductively coupled plasma, which is ultimately correlated with a higher UV/VUV emission.

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm- $L_{g}$ device shows a peak $g_{m}$ of $1.37 \ \text{mS}/\mu \mathrm{m}$ , a subthreshold slope in saturation of 72 mV/decade, and an $I_{on}$ of $355 \ \mu \mathrm{A}/\mu \mathrm{m}$ at 0.5 V $V_{gs}$ , the highest among reported sub-50 nm- $L_{g}$ III-V FETs on Si.

For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.

The resistivity of damascene Cu is measured at cross-sectional area as low as 95 nm2. The impact of aspect ratio and line edge roughness on resistivity is investigated. Kelvin resistance test structures are demonstrated with 28 nm pitch wires patterned by directed self-assembly of lamellar block copolymers. The effective resistivity of TaN/Ta/Cu wires is compared with alternative metals.

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Directed self-assembly (DSA) with block-copolymers (BCP) is a promising lithography extension technique to scale below 30nm pitch with 193i lithography. Continued scaling toward 20nm pitch or below will require material system improvements from PS-b-PMMA. Pattern quality for DSA features, such as line edge roughness (LER), line width roughness (LWR), size uniformity, and placement, is key to DSA manufacturability. In this work, we demonstrate finFET devices fabricated with DSA-patterned fins and compare several BCP systems for continued pitch scaling. Organic-organic high chi BCPs at 24nm and 21nm pitches show improved low to mid-frequency LER/LWR after pattern transfer.

The need for continued device scaling along with the increasing demand for high precision have lead to the development of atomic layer etch processes in semiconductor manufacturing. We have tested this new methodology with regard to patterning applications. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. While PE-ALE approaches seem to have limited success for trilayer patterning applications, significant improvements were obtained when applying them to small pitch. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

Linear transparent zinc oxide films were fabricated using an inductively coupled microplasma jet generated in argon under atmospheric conditions. The films were formed by the sputtering and melting of a zinc filament placed inside the plasma. Film growth rates varied between 10 to 30 nm/s for input powers between 20 and 30 W. Film roughness below 20 nm and optical transmittances up to 90% in the visible were obtained while the sheet resistances ranged between 2 × 104 and 1 × 105Ω/□. The presented technique may allow high-rate, localized, fabrication of functional ZnO films for optoelectronic applications.

Local coinjection of a (H2–Ar) microplasma jet and Cu(O2C5F6H)2 molecules during focused electron beam-induced deposition (FEBID) was studied with respect to changes in the Cu:C ratio of deposits. Microplasma-assisted FEBID (30 keV and 1 nA) decreased codeposition of carbon, oxygen, and fluorine originating from the chamber background and the precursor molecule. The copper metal content could be increased to 41 at. %, being almost four times more than in conventional FEBID deposits without coinjection. Conventional FEB deposits from Cu(O2C5F6H)2 resulted in 11–12 at. % Cu content. Microplasma post-treatments of conventional FEB deposits resulted in volume changes, surface roughening, and an increase of the overall Cu content to 27 at. %. The removal mechanisms were of nonthermal nature. At repulsive bias potentials from 0 to +30 V, a pure chemical etching of the carbonaceous matrix by atomic hydrogen radials occurred. At attractive bias potentials of up to −30 V, a more efficient ion induced chemical sput...

A novel etch chemistry, C4H9F was evaluated for highly selective patterning of SiN using both organic and SiOx masks for line/space and cylindrical geometries. Patterning of 80 nm of SiN using 65 nm of the organic planarization layer (OPL) mask with a C4H9F:O2:CF4 admixture yielded line edge roughness (LER) and line width roughness (LWR) values of 1.9 and 2.8 nm on sub-25 nm critical dimension (CD) SiN lines at 50 nm pitch, with >50 nm mask retention up to 40% overetch values. The LER and LWR values were 60% and 66% lower than features patterned using a CF4:CHF3 admixture, which also exhibited complete OPL mask loss and nitride erosion of 27 nm even at the endpointed etch condition. Using 20 nm of SiOx as a mask and removing CF4 from the chemistry admixture, LER and LWR values of 2.7 and 3.3 nm were achieved with nearly full SiOx retention for features of identical dimensions. At smaller mask pitches (21 and 24 nm) formed by directed self-assembly of high-χ block copolymers, the highly selective nature of C4H9F to organic masks facilitated SiN pattern transfer where CF4 based admixtures failed, achieving line CDs of ∼12 nm with LWR and LER of 1.6 and 2.2 nm. Applied to alternate geometry, hole patterning in SiN at ∼30 nm CD and 60 nm pitch was demonstrated. A subsequent image reversal process yielded pillars by filling the hole pattern with OPL and etching back the surrounding SiN layer, reaffirming the extremely high selectivity of C4H9F to organic masks.A novel etch chemistry, C4H9F was evaluated for highly selective patterning of SiN using both organic and SiOx masks for line/space and cylindrical geometries. Patterning of 80 nm of SiN using 65 nm of the organic planarization layer (OPL) mask with a C4H9F:O2:CF4 admixture yielded line edge roughness (LER) and line width roughness (LWR) values of 1.9 and 2.8 nm on sub-25 nm critical dimension (CD) SiN lines at 50 nm pitch, with >50 nm mask retention up to 40% overetch values. The LER and LWR values were 60% and 66% lower than features patterned using a CF4:CHF3 admixture, which also exhibited complete OPL mask loss and nitride erosion of 27 nm even at the endpointed etch condition. Using 20 nm of SiOx as a mask and removing CF4 from the chemistry admixture, LER and LWR values of 2.7 and 3.3 nm were achieved with nearly full SiOx retention for features of identical dimensions. At smaller mask pitches (21 and 24 nm) formed by directed self-assembly of high-χ block copolymers, the highly selective nature of...

The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These unique characteristics of C4H9F can facilitate innovative plasma etch processes for nitride-based materials patterning in a wide range of applications.The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These uniq...

Two approaches were applied to thermal plasma spray chemical vapor deposition (TPS CVD) in order to reduce crystal grain size or/and surface roughness of LiNb 0.5 Ta 0.5 O 3 thin films while retaining the advantages of this method, such as high deposition rate. The first method consists of a two-step deposition, where the nucleation density is controlled in the first step and the film with high crystallinity is deposited in the second step. The surface roughness and grain size could be reduced from 1 nm to 7.7 nm, and from 200–350 nm to 120–180 nm, respectively. In the second approach, employing a one-step TPS CVD process, the conventional precursor was substituted by a double-alkoxide precursor and grain size in the deposited films could be reduced to 50–80 nm. Both approaches adopted in this work permitted to reduce the optical propagation loss.

We present the first realization of a monolithically integrated piezoelectronic transistor (PET), a new transduction-based computer switch which could potentially operate conventional computer logic at 1/50 the power requirements of current Si-based transistors (Chen 2014 Proc. IEEE ICICDT pp 1-4; Mamaluy et al 2014 Proc. IWCE pp 1-2). In PET operation, an input gate voltage expands a piezoelectric element (PE), transducing the input into a pressure pulse which compresses a piezoresistive element (PR). The PR resistance goes down, transducing the signal back to voltage and turning the switch 'on'. This transduction physics, in principle, allows fast, low-voltage operation. In this work, we address the processing challenges of integrating chemically incompatible PR and PE materials together within a surrounding cage against which the PR can be compressed. This proof-of-concept demonstration of a fully integrated, stand-alone PET device is a key step in the development path toward a fast, low-power very large scale integration technology.

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.

A viable pattern customization strategy is a critical to continue fin pitch scaling. Analysis shows that a self-aligned customization scheme will be required for fin pitch scaling beyond 20nm. In this paper, we explore scaling of the Tone-Inverted Grapho-Epitaxy technique with 24nm pitch PS-b-PMMA polymer to create groups of fins with self-aligned spaces in between. We discuss material selection, self-aligned customization, and etch processes to form 24-nm-pitch fins on silicon on insulator substrates. We demonstrate two-dimensional pattern customization at 24nm pitch, confirming scalability of this approach. FinFET device integration results at both 28 and 24 nm pitches shows a promising path for continued fin pitch scaling.

The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing., Comment: in Nano Letters (2015)

Thin lithium niobate-tantalate (LiNb0.5Ta0.5O3) films are studied at the initial stage of deposition from a thermal plasma. The effect of two deposition parameters (the substrate temperature and the deposition rate) on the film morphology, the film crystallinity, and the density of nuclei growing on a (0001) sapphire substrate are investigated. It is shown that the crystalline structure and roughness of a film are determined, for the most part, in the initial growth stage and therefore depend directly on both parameters. At the optimum temperatures and growth rates for obtaining good characteristics of (0006) texture, crystallinity, and surface roughness of the films, the film nuclei on the substrate have a high density and good epitaxial orientation to it. If the growth conditions are not optimum, the islands are either amorphous or have a low density on the substrate surface. The nucleation activation energy is observed to decrease as the deposition rate increases, which supports the assumption that the species that are active in film deposition are “hot” clusters forming in an oxygen-argon plasma in the immediate vicinity of the substrate.

Processing with atomic layer precision requires the ability to not only add, remove or modify one monolayer of material but to also leave adjacent layers unchanged. This requires fine control over the flux of species and energy deposition at the surface. The appropriate threshold and process windows are certainly material specific but it is reasonable to assume many applications require low energy ions. Electron beam-generated plasmas are generally characterized by high charged particle densities (1010- 1011 cm-3), low electron temperatures (0.3 - 1.0 eV), and in reactive gas backgrounds, a relatively low radical production rate compared to discharges. The flux at the surface will thus be characterized by a comparatively large amount of ions whose energies are < 5 eV, a value commensurate with the bond strength of most materials. As such, these sources are well-suited to explore processing space not commonly found in industrial tools. In this work, we discuss SiN etching using pulsed, electron beam generated plasmas produced in SF6 backgrounds. We pay particular attention to the etch rates, selectivity (vs. carbon films, Si and SiO2), and patterning as function of operating parameters such as relative gas concentration, operating pressure, and substrate bias. These results are compared with plasma diagnostics to gain a better understanding of the process requirements and windows for threshold etching of SiN. This work is partially supported by the Naval Research Laboratory base program.

Deformation of the pattern or the increase in line roughness during plasma etching becomes more significant with the shrink of complementary metal–oxide–semiconductor patterns. For aggressively scaled patternings, an organic underlayer (UL) is often used under the photoresist and a thin layer of a Si-containing hardmask. In this work, the effect of ultraviolet/vacuum ultraviolet (VUV) photons on UL parameters such as wavelength, photon dose, and process order was investigated using synchrotron radiation. First, the index of refraction and extinction coefficients of mask materials such as e-beam resist [hydrogen silsesquioxane (HSQ)] and organic UL (NFC-1400; NFC) were measured by utilizing the Kramers–Kronig relations and/or ellipsometry measurements depending on the wavelength involved. Second, VUV photons at specific wavelengths, corresponding to absorption maxima of HSQ and NFC at 54 nm (HSQ), 62 nm (HSQ and NFC), 88 nm (HSQ), 112 nm (NFC), 138 nm (HSQ), 155 nm (NFC), 194 nm (NFC), and 238 nm (NFC), we...

We propose a very selective PMMA removal method from poly(styrene-block-methyl methacrylate) (PS-b-PMMA) copolymer using gas pulsing cyclic etching. Flow ratio of hydrogen (H2) added to carbon monoxide (CO) plasma was periodically changed to control etch and deposition processes on PS. By controlling the process time of each etch and deposition step, full PMMA removal including etching of the neutral layer was demonstrated at 28 nm pitch, while PS thickness remained intact. This is more than 10 times higher etch selectivity than conventional continuous plasma etch processes using standard oxygen (O2), CO–H2 and CO–O2-based chemistries.

In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.

Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential of this process for circuit relevant patterning continues to be a major challenge. In this work, we propose a way to impart two-dimensional pattern information in graphoepitaxy-based lamellar phase DSA processes by utilizing the interactions of the BCP with the template pattern. The image formation mechanism is explained through the use of Monte Carlo simulations. Circuit patterns consisting of the active region of Si FinFET transistors, referred to as Si “fins”, were fabricated to demonstrate the applicability of this technique to the formation of complex patterns. The quality of the Si fin features produced by this process was validated by demonstrating the first functional DSA-patterned FinFET devices with 29 nm-pitch fins.

The information age has produced astonishing improvements in compute power, but the current highly successful CMOS technology is running into power limitations. Computing takes up of order 5% of the US electricity production, power is now the primary limiting factor on clock speed, and power limits practical development of exascale computing facilities. CMOS power depends on voltage which is now limited by fundamental physics and cannot be further lowered by an engineering fix. A fundamentally new device concept is needed in order to take computing into a new lower power regime.

As 14nm node devices begin to permeate into the semiconductor industry, it is becoming increasingly evident that continued pitch scaling is getting more complex throughout the FEOL, MOL and BEOL. The adoption of patterning schemes and pitch splitting techniques such as double exposure/double etch and sidewall image transfer (SIT) are already underway to extend 193nm immersion lithography and enable 3D FinFET / Trigate devices. In addition, BEOL scaling of damascene copper is facing its own challenges, between the patterning and integration of porous ULK materials and the issue of increased resistivity emanating from grain boundary and surface scattering. As such, this paper will present work on novel etch methods envisioned to enable the successful extension of patterning and device integration for the 10nm node and beyond. Work related to the exploration of novel feedgas chemistries to extend etch performance for SiN spacer and oxide etch applications will be reviewed in detail. Specifically, the realization of a silicon nitride etch process which no longer depends on an oxidation mechanism, but rather a polymerization based etch mechanism will be shown. The process exhibits high selectivity to SiO2, Si and photoresist and results in reduced SOI loss while simultaneously maintaining all SiN on the gate sidewall and significantly reducing SiN footing. In addition, the feasibility of novel patterning methods such as the introduction of subtractive etching of copper will be reviewed in detail. Subtractive etching of Cu has the potential to overcome current interconnect integration difficulties by enabling blanket Cu film deposition with large grains, and by minimizing plasma damage during ULK etch, respectively. Successful patterning of copper at 25-50nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process.

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant pat- terning in the sub-30-nm pitch regime using directed self-assembly (DSA) line-space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck tem- perature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal-oxide-semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node. © 2013 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.12.4 .041305)

The ability to achieve atomic layer precision is the utmost goal in the implementation of atomic layer etch technology. Carbon-based materials such as carbon nanotubes (CNTs) and graphene are single atomic layers of carbon with unique properties and, as such, represent the ultimate candidates to study the ability to process with atomic layer precision and assess impact of plasma damage to atomic layer materials. In this work, the authors use these materials to evaluate the atomic layer processing capabilities of electron beam generated plasmas. First, the authors evaluate damage to semiconducting CNTs when exposed to beam-generated plasmas and compare these results against the results using typical plasma used in semiconductor processing. The authors find that the beam generated plasma resulted in significantly lower current degradation in comparison to typical plasmas. Next, the authors evaluated the use of electron beam generated plasmas to process graphene-based devices by functionalizing graphene with...

With increasing demands on device patterning to achieve smaller critical dimensions and pitches for the 5 nm node and beyond, the need for atomic layer etching (ALE) is steadily increasing. In this work, a cyclic fluorocarbon/Ar plasma is successfully used for ALE patterning in a manufacturing scale reactor. Self-limited etching of silicon oxide is observed. The impact of various process parameters on the etch performance is established. The substrate temperature has been shown to play an especially significant role, with lower temperatures leading to higher selectivity and lower etch rates, but worse pattern fidelity. The cyclic ALE approach established with this work is shown to have great potential for small scale device patterning, showing self-limited etching, improved uniformity and resist mask performance.

While proven to provide high performance at sub-10 nm lengths, carbon nanotube (CNT) field-effect transistors (FETs) typically employ impractical gate geometries. Here we demonstrate fully self-aligned CNTFETs that include a gate-all-around (GAA) the nanotube channels — the ideal gate geometry for a 1D CNT. These GAA-CNTFETs have 30 nm channel lengths and exhibit n-type operation with high on-currents and good switching behavior that is explained by quantum transport (NEGF) simulations. This work is an important milestone showing that a technologically relevant self-aligned device can be realized with nanotubes.

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.

Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents the successful pattern transfer into the substrate. In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer performance. This allowed us to systematically study material, substrate and etch process parameters and draw conclusions about how changes in these parameters may improve the overall pattern transfer margin.

In this work, the control of focused ion beam induced deposition (FEBIE) process is examined through fabrication of nanoholes on 10-nm-thin amorphous carbon (a-C) membrane using H2O and XeF2 precursor, and its in-situ stage current measurement. Nanoholes with diameters smaller than the beam size were successfully obtained. Results indicate the feasibility of fabrication of nanoholes with sub-nm diameter in the future.