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In this study, we attempted to classify the sex of salmon using a convolutional neural network. We collected labeled(male/female) images of salmon and other fishes, and trained the VGG16 type neural network by implementing several data argumentation techniques, cropping the bounding box of salmon. In evaluation, the F value of the classification result was found to be satisfactory by more than 99%. We demonstrated the focus point of the neural network using Grad-CAM and the classification ability depending on the background processing.

In this paper, we describe the details of the design and implementation of our Front-end Environment for Hands-on Activities (FEHA), which is a web-based programming environment. FEHA provides a programming environment on the web and utilizes existing Unix-like systems that equip a specialized programming environment as the build and runtime platform. FEHA controls the existing systems by using Secure SHell (SSH) and Rsync without any modification of the existing systems. We discuss a case study of FEHA in which it was applied to actual programming lectures at a university. In the lectures, 70% of the students completed registrations to use FEHA in about 3 min. In addition, they could understand how to use the FEHA and started submitting codes within several minutes after the registration. The case study shows that FEHA is able to provide a specialized programming environment for more than 100 students with a small amount of effort from the instructor and system administrator.

We develop a visualization tool for designing a topology-aware communication algorithm. This tool visualizes the communication behavior from the logs of a network simulator or an existing parallel computer. Using multiple views, filtering functions, and an animation function, the tool affords users an intuitive understanding of communication behavior and provides statistical information. The topology view represents the spatial load distribution of the network topology in 3D space. The user can analyze the communication behavior on a specific network topology. A distinction between the behaviors of the new all-to-all communication algorithm and the conventional one is drawn clearly by the tool. In addition to the poster presentation, we are going to present a communication algorithm behavior on PC using our visualization tool.

An efficient all-to-all communication algorithm for torus and mesh networks, A2AT, was proposed. A2AT schedules message sending sequence so that all links are fully used by exploiting function of concurrent message transfer in the node. By using A2AT, the hop count of messages equals the maximum number of messages sharing a link in their routes for all message transfers. A2AT can therefore maintain synchronization without the need for phasing operation such as an MPI barrier. When the VOQ which is an ideal configuration for A2AT was used, communication times for mesh/torus network obtained by A2AT were roughly 1.20 and 1.09 times higher, on average, than those of the ideal times. When the networks had the minimum number of virtual channels and a small buffer, assuming a practical network, A2AT was able to reduce communication times by 12.5% and 36.0% compared with those of the conventional algorithm. When two controllers are used, A2AT reduced 28.2% and 55.7% communication time with those by A2AND on 15x15x15 (=3,375 nodes) mesh and torus networks respectively (18.6% and 44.8% in average). A2AT also reduced 15.1% and 41.9% of communication time with those by A2AND on the same mesh and torus networks respectively (14.4% and 37.5% in average) when six controllers are used.

The aim of this study is to apply the unprecedented high-speed computing made possible by parallel processing to a wide range of problems such as computer graphics. A highly parallel cellular array processor, the CAP-256 has been developed in which 256 high-performance processors, called cells, are connected together. The CAP-256 includes a function by which a generated image is displayed in real-time, as well as a function to construct various kinds of [inter-processor] communication networks (topologies). A VLSI chip has been developed which integrates the communication and synchronization functions required for parallel processing, as well as the I/O function for the image. Using this VLSI chip, the cell was implemented in a compact form, and a small-sized high-performance parallel computer was implemented. To operate the cell, software called the cell OS (operating system) was developed. The software environment which has been implemented makes it possible to easily develop and efficiently execute application programs based on message communication. An image was generated using parallel ray-tracing which has three to four times higher performance than that of the general-purpose FACOM M-380 mainframe computer. The authors are also attempting to develop applications for CAD problems such as automatic wiring as well as scientific calculations. The versatility of the CAR-256 has been verified.

This paper proposes and evaluates an algorithm of parallel matrix multiplication on compressed sparse‐matrices. In addition to that, to overcome the problem of imbalanced distribution of non‐zero elements over processors, a technology for dynamic load‐balancing is examined. Measurements of the performance show that the algorithm achieves sufficient speed up. The experiments in this paper could not show the significant effect of the dynamic load‐balancing. It requires more analysis to determine the reason of this.

Low-latency communication is the key to achieving a high-performance parallel computer. In using state-of-the-art processors, we must take cache memory into account. This paper presents an architecture for low-latency message comunication and implementation, and performance evaluation. We developed a message controller (MSC) to support low-latency message passing communication for the AP1000, to minimize message handling overhead. MSC sends messages directly from cache memory and automatically receives messages in the circular buffer. We designed communication functions between cells and evaluated communication performance by running benchmark programs such as the Pingpong benchmark, the LINPACK benchmark, the SLALOM benchmark, and a solver using the scaled conjugate gradient method.

A highly parallel computer with distributed memory called the AP1000 has been developed. The system consists of 64 and 1024 processing elements and three independent networks called the torus network (T-net), broadcast network (B-net), and synchronization network (S-net). The design goal for the AP1000 is to attain low-latency, high-throughput communication. To reduce the overall communication latency, a message controller and a new routing scheme on the T-net have been developed. The design concepts, architecture, and some results from performance tests for the AP1000 are presented. >

The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.

The general-purpose cellular array processor (CAP) we developed features multiple-instruction stream multiple-data stream (MIMD) processing and image display. Several hundreds of processor elements can be connected together. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common interfaces for data broadcasting and six 15M bit/s serial communication ports for local data communication. The chip can also process image data in real time for multiple processors.

A general purpose Cellular Array Processor(CAP) with distributed frame buffers for fast parallel subimage generation has been developed. CAP consists of many processor elements called cells. A cell has video memory for subimage storage, a window controller to map each subimage to an area on the monitor screen, and communication devices, in addition to ordinary microcomputer components such as MPU, RAM, and ROM. Image data in a cell is directly displayed via the video bus. The mapping pattern and the position on the screen of subimages can be changed dynamically. Various hidden surface algorithms can be implemented in CAP using mapping patterns appropriate for the algorithm.Our goal is an efficient interactive visual solid modeler. We adopted a general CSG hidden surface algorithm that enables display of both Boundary representation and Constructive Solid Geometry. A technique for hidden surface removal of general CSG models, requiring less memory space for large models in many cases, has been proposed. This technique subdivides the model into submodels by dividing the CSG tree at union nodes. Imagse of each submodel are generated by a CSG or a z-buffer algorithm. If a submodel is just a primitive, it is processed by the z-buffer algorithm, otherwise by the CSG algorithm. Hidden surface removal between submodels is done by comparing the z values for each pixel which are saved in the z-buffer.