Search

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

In this work, we report on the fabrication of all-implanted β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) devices on semi-insulating (-201) β-Ga2O3 substrates. Through the use of multiple energy Si+ implantation and subsequent annealing, we were able to achieve high activation efficiencies up to 87% allowing to realize the active transistor channel and Ohmic contact regions with electrical properties comparable to homoepitaxial layers grown by metal-organic chemical vapor deposition. The fabricated β-Ga2O3 MOSFET devices featured excellent current modulation with on/off current ratios up to 109, maximum drain current densities of 180 mA/mm, and specific on-resistances of 1.5 mΩcm2. Furthermore, breakdown measurements in air of the non-field-plated MOSFET devices with a gate-to-drain distance of 2 μm showed a catastrophic breakdown at 332 V, which equals an average breakdown strength of 1.7 MV/cm. The outcome of this work emphasizes the high potential of this all-implantation approach for fabricating high-performing Ga2O3-based electronic devices for next-generation power electronics applications without the need of sophisticated high-quality epitaxial growth. [ABSTRACT FROM AUTHOR]

The development of processes for epitaxial growth of vertical gallium nitride (GaN) drift layers enabling 1.2 kV breakdown voltage on low‐cost sapphire substrates is presented in comparison to GaN bulk substrates. The targeted blocking capability demands drift layers with a thickness of 10 μm and low but controllable n‐type doping. Using a growth rate of 2.5 μm h−1 the concentration of unintentionally incorporated carbon is sufficiently low to adjust the n‐type carrier concentration to ≈1 × 1016 cm−3 for all types of substrates. To assess GaN drift region properties in terms of forward bias conductivity and reverse bias blocking strength, a quasi‐vertical p‐n‐diode structure is utilized. Bow reduction of GaN‐on‐sapphire structures is achieved using a stealth laser scribing process. Breakdown voltages higher than 1600 V and a specific on‐state resistance as low as 0.7 mΩ cm2 are obtained with diodes fabricated on GaN substrates. Similar structures grown on sapphire show breakdown voltages of about 1300 V due to higher levels of current leakage. Comparing different types of substrates, a direct correlation between dislocation density in the drift layer with the leakage current in p‐n diodes is deduced. [ABSTRACT FROM AUTHOR]

In this work, we analyze the optimum annealing conditions for the activation of Ge-implanted β-Ga2O3 in order to reach low ohmic contact resistances. The experiments involved the use of a pulsed rapid thermal annealing treatment at temperatures between 900 and 1200 °C in nitrogen atmosphere. Our investigations show remarkable changes in the surface morphology involving increased surface roughness after high-temperature annealing above 1000 °C as well as a significant redistribution of the implanted Ge. Nevertheless, the specific contact resistance is strongly reduced by one order of magnitude after annealing at 1100 °C, reaching a record value of 4.8 × 10−7 Ω cm2 at an implantation activation efficiency of 14.2%. The highest activation efficiency of 19.2% and lowest sheet resistances were reached upon annealing at 1200 °C, which, in turn, showed inferior ohmic contact properties due to a severe increase of the surface roughness. Our results verify the high potential of applying high-temperature annealing processes above 1000 °C after Ge implantation for reaching low ohmic contact resistances to β-Ga2O3. [ABSTRACT FROM AUTHOR]

An enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility-transistor devices by increasing the electron confinement in the transistor channel is described by using an AlGaN buffer-layer structure. The beneficial properties are pronounced if gate-recess technology is applied for device fabrication and physical-based device simulations have given insight in the respective electronic mechanisms.

Vertical silicon carbide transistors and lateral gallium nitride (GaN) transistors for power-electronic applications currently target applications with different voltage and power ratings. Meanwhile, research and development activities continue on vertical GaN transistors and new gallium oxide (Ga2O3) transistors. What are their perspectives in the application and how do they compete against each other and against established transistor technologies? This study discusses the specific characteristics of lateral and vertical GaN and Ga2O3 transistors to assess their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

In this work, a vertical n‐channel MISFET homoepitaxially grown on ammonothermal n‐type GaN substrates by MOVPE is demonstrated. The MIS gate module consists of plasma enhanced atomic layer deposition of Al2O3 combined with in‐situ NH3 plasma surface pre‐treatment. An annealing step performed at 350 °C in N2 ambient drastically improves device performance. It reduces the ON‐state resistance from ≈12.0 k Ω mm to ≈150 Ω mm, increases the ON‐OFF ratio from 106 to 108, and lifts up Ids_max from  ≈ 0.25 to ≈ 40 mA mm−1. The threshold voltage is above +5 V and the median vertical off‐state blocking voltage strength is ≈68 V μm−1. Accumulated C–V characterization of planar MIS‐capacitors on n‐GaN gives insight to mechanisms boosting device performance after annealing. [ABSTRACT FROM AUTHOR]