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Scaled ferroelectric transistors (L g =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor channel to reduce parasitic interfaces. As a result, ferroelectric transistors with 3σ memory window for fast programming time of 10 ns (including an instantaneous read-after-write) at 1.8 V and high endurance of 1012 cycles are demonstrated for the first time.

AI (Artificial Intelligence) is all about possessing a high volume of unstructured data and then needing to process it at high speed. DRAM today is the technology of choice for memory in such AI systems. Yet, DRAM’s high energy per bit and the diminishing scaling of DRAM represent a real challenge for the AI system’s future. This chapter covers solutions utilizing technologies similar to those currently used in 3D NAND for high speed memory.

The design issues in CMOS at Nano meter levels has increased the demand for post-CMOS technologies. Quantum-dot Cellular automata is one of the promising post-CMOS technology that can be used in the near future. It is a transistor-less nanotechnology paradigm that has the competence to design high speed and low power Nanoscale circuits with higher packaging densities. Data integrity is a key factor in the design of any memory storage device. In this paper, a novel memory cell architecture is proposed in QCA. The proposed design has more data integrity compared to the existing designs. Simulation results shows that the proposed design has higher speed compared to the existing designs. The proposed memory cell can be extended to implement any large size memory circuit in QCA. QCADesigner 2.0.3 is used for the validation of the proposed design in QCA.

This paper reviews some of the evidence that bears on the existence of a mental high-speed serial exhaustive scanning process (SES) used by humans to interrogate the active memory of a set of items to determine whether it contains a test item. First proposed in the 1960s, based on patterns of reaction times (RTs), numerous later studies supported, elaborated, extended, and limited the generality of SES, while critics claimed that SES never occurred, that predictions from SES were violated, and that other mechanisms produced the RT patterns that led to the idea. I show that some of these claims result from ignoring variations in experimental procedure that produce superficially similar but quantitatively different RT patterns and that, for the original procedures, the most frequently repeated claims that predictions are violated are false. I also discuss evidence against the generality of competing theories of active-memory interrogation, especially those that depend on discrimination of directly accessible “memory-strength”. Some of this evidence has been available since the 1960s but has been ignored by some proponents of alternative theories. Other evidence presented herein is derived from results of one relevant experiment described for the first time, results of another described in more detail than heretofore, and new analyses of old data. Knowledge of brain function acquired during the past half century has increased the plausibility of SES. The conclusion: SES is alive and well, but many associated puzzles merit further investigation, suggestions for which are offered.

The current challenge is to meet out the compatibility of data rates between the data processing systems and the memory bandwidth requirements. For a stream oriented data, Double Data Rate Type three (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) memory interface boosts the buffering capability for processing applications. In this paper, We mainly focus on optimizing the throughput of a high speed DDR3 memory interface using the Advanced eXtensible Interface (AXI) protocol containing independent read/write channels. We have designed the user defined logic in the AXI master to command the AXI slave viz., DDR3 memory. The final design is implemented in the Microsemi RTG4 series FPGA and operated at the frequency of 320 MHz. The design is articulated to achieve maximum throughput by designing AXI master without write response states.

This paper discusses multi-point address channel design in fly-by topology for high speed memory interface. Waveform behaviors at DRAM locations along the channel are examined in depth with eye opening data in various channel design factors and device termination settings. Eye opening is exacerbated on the front DRAM from the controller more prominently due to ring-backs from high frequency reflections at the node while eye opening at DRAMs along mid-channel is more notably affected by dual eye tracks from effective channel impedance to termination mismatch as well as high frequency loss from DRAM nodes of channel front. Channel design is explored for overall channel performance improvement to consider different waveform behaviors at address input nodes of multiple DRAMs along the channel and design suggestions are developed.

At room temperature, cubic SrTiO3 perovskite exhibits only paraelectric property, although ferroeletric properties appear in tetragonal BaTiO3 and PbTiO3. In this study, the new high-performance ferroelectric such as SrTiO2C perovskite was theoretically designed. Cluster model calculations based on hybrid density functional theory were performed to clarify a ferroelectric mechanism of SrTiO2C. It has been concluded that SrTiO2C can be utilised for a ferroelectric material of a high-speed memory, due to the extremely small polarisation-inversion energy.

Nowadays, high speed memory systems having large capacity use high-density RAM chips with wide I/O data. These chips are prone to multiple random bit errors (known as m -spotty byte errors) when encountered with high energy particles. To detect or correct such errors, a new class of error-control codes called byte error-control codes have been introduced and studied. In this paper, we define and study a g -fold joint m -spotty Lee weight enumerator of byte error-control codes over the ring of integers modulo l ( l ≥ 2 an integer) and over arbitrary finite fields. We also derive some MacWilliams type identities for this enumerator.

This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.

The author examines how Rambus' revolutionary technology and marketing savvy have put this small chip company on the map-and offended some of the biggest name in the business. The legal problems surrounding the high-speed memory interface technology manufacturer are also outlined.

In this paper, we investigate and quantify fiber weave effects on state-of-the-art high speed memory and SerDes (serialization-deserialization) interfaces. It has been discussed that the fiber weave effects in embedded systems do not pose a risk because typical trace lengths are short. We demonstrate that even in such cases, fiber weave effects can consume valuable timing margin in high speed channels. For this analysis, we consider the micro-scale composition of PCB laminates in order to create realistic two- and three-dimensional models incorporating fiber weave effects. We then assess the fiber weave effect impact on the quality and integrity of high speed signals on typical memory and SerDes channels on a PCB design targeting a generic mobile platform. Specifically, we investigate the potential risk that fiber weave effects can present in high speed SerDes channels. Two primary effects are investigated: time skew on DRAM systems and intra- and inter-pair skew in SerDes channels. Both effects are the result of local variations of the dielectric characteristics of the PCB substrate with position. In addition, we briefly discuss the underlying physical mechanisms originating these problems and review the pros and cons of mitigating techniques.

The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

A high-speed memory system is a complex mixed-signal design including controller, memory, board design. For realistic simulation, all the non-idealities i.e. noise, crosstalk should be modeled to fulfill the jitter, setup-hold specifications. Matlab/Simulink provides customizable components for noise sources, statistical models and communication blocks. Besides, Matlab/Simulink provides early validation of the system behavior without the need of a higher refinement level, which reduces the design time. This paper proposes an efficient methodology which can be applied to mixed-signal design based on Matlab/Simulink-HDL co-simulation. To illustrate the proposed method, the development of memory system is chosen as a case study.

The interconnect margins shrink rapidly at higher speed due to reduced bit width and increased noise level. Crosstalk impact remains the biggest concern for the single-ended memory busses such as DDR3 and GDDR5 interconnect. The phase relationship of the xtalk coupling plays an important role on interconnect performance. This paper outlines several types of off-phase crosstalk and their impact to system margin. It also provides the methodology to analyse their effects and design considerations to mitigate their impact.

In this paper, two-stage NIDS architecture is proposed, which aims to both increase the throughput and reduce memory cost. The contributions of this work are listed below.

Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.

This is a comparative study for varied type package performance. From the study, we are able to quantify the performance by parasitic parameter, bandwidth, voltage swing of Vref and skew simulation results.

By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant DDR II component. It can be seen that the cost advantages of PCB-like CiSP and the electrical performance of WLP can be achieved simultaneously by adopting this proposed solution. A test vehicle of DDRII-667 memory chips provided by ProMos Technologies Inc. was studied here to demonstrate the feasibility of this developed packaging. Compared with the type I CiSP and the current w-BGA package, the performance is thermally and electrically enhanced.

We introduced the novel porous low-k material with k~2.3 improved the physical properties for intermetal dielectric application in high speed memory device. Because this low-k material has both Si-H and Si-CH 3 bonds in its SiO2 film, it reduced the bowing and adhesion failure of P-HSQ and P-MSQ at via profile and metal wire. As this material was applied at device, the parasitic capacitance between metal wires was reduced till 20% compared with that of the HSQ

We have proposed the charge-share modified precharge-level architecture with self-timing precharge technique. It is a low-power dissipation architecture for achieving high-density, high-speed, and high-operating-margin simultaneously, making it a leading candidate for use in an Mb-scale ferroelectric memory.

A partial-response detection technique cuts the driver power by up to 85% in memory-to-processor communication with several hundred MHz data rates. The signaling scheme reduces driver power by reducing the transistor width and raising the termination resistance above the the characteristic impedance. This results in a reduction of the signal bandwidth and thus a large inter-symbol interference (ISI). This side effect is offset by detecting the partial response of the transmitted signal, in which the ISI is subtracted from the signal. The receiver samples the data at half-periods of the clock. It employs a delay-locked loop to time sampling at the end of each symbol period of length T, to fully exploit signal current integrated in the signaling line during that period.

We described the case of a 59 year old female with transient global amnesia (TGA) who had been examined neuropsychologically using Sternberg's paradigm and a random number generation (RNG) task on the following day, 1 week and 4 weeks after a TGA episode. The slope value of the linear function, a measure of cognitive memory scanning speed, decreased with time and showed a marked decrease 1 week after TGA, suggesting that the stage of serial and exhaustive scanning recovered within 1 week. The zero-intercept value, on the other hand, increased during 1 week but decreased 4 weeks later and was not related directly to recovery from TGA. The performance in RNG task improved 1 week later, but deteriorated 4 weeks after the episode. Such a change in RNG was in accordance with that of the zero-intercept value, predicting a relationship. It is concluded that the subclinical memory deficit, detected with these tasks, persisted longer than clinical recovery from TGA.

Bulk AgI based fast ion conducting (FIC) glasses have been prepared by a novel microwave technique. Electrical switching characteristics of these glasses have been investigated for the first time. It has been found that AgI based FIC glasses exhibit a current-controlled high speed memory electrical switching behaviour. SEM, EDAX and ESR investigations have been performed on the virgin and switched sampies to understand the nature of the conducting state. A chemical model is proposed to explain the switching behaviour of these glasses, which is consistent with the observed results.

THERE IS A LIMITIED amount of knowledge, practice, and aspiration which is currently manifested in the thoughts and activites of contemporary mathematicians. The mathematics that is frequently used or is in the process of emerging is part of the current consciousness. This is the material which—to use a metaphor from computer science—is in the high speed memory or storage cells. What is done, created, practiced, at any given moment of time can be viewed in two distinct ways: as part of the larger cultural and intellectual consciousness and milieu, frozen in time, or as part of a changing flow of consciousness.

Experimentation with unilateral and bilateral tachistoscopic stimulation (the Dimond paradigm) increasingly suggests that interhemispheric cooperation (bilateral advantage) occurs or increases as a function of task complexity in general and memory load in particular. However, tachistoscopic experimentation with ipsilateral and contralateral field/hand relation conditions (the Poffenberger paradigm) has failed to provide any conclusive supporting evidence. The present investigation comprised a Sternberg "high speed memory scanning" task, modified as a go/no-go task, and formatted into the Poffenberger paradigm. Sets of items to be scanned (memory load) varied in size from one to four. A highly significant effect of load and a significant field/hand interaction were found, but the field/hand/load interaction did not reach significance. We concluded that the interhemispheric transfer time (ITT) metric drawn from this paradigm is not reliably sensitive to increasing memory load. However, our finding of significantly longer ITT in women than in men suggests that commissural anatomy and physiology may be sexually dimorphic.

Many high-data-rate experiments in elementary particle physics suffer large dead-times due to the slow speeds with which the on-line computer can read in data from each event. To eliminate this bottle-neck, we have designed, constructed, and made extensive use in a physics experiment of a 4 megabyte memory buffer which employs ordinary dynamic RAM memory chips and which accepts all of our event data generated during a beam spill at Fermilab at a rate of 14 Mbyte per second.

This study tested the hypothesis that the slowing seen in parkinsonism includes cognitive as well as motoric components. The sample consisted of 20 nondemented parkinsonian patients, group matched to 16 normals by age, education, and verbal IQ. Each group was divided into young (64 and under) and old (65 and over) subsets. The Sternberg character classification paradigm was used to measure the speed and accuracy of one cognitive function, short term memory scanning. Following a logarithmic transformation of the reaction time data, scanning speed was found to be increased, but only for the elderly patients (p = .01). Scanning accuracy was normal for both patient groups. These findings suggest that at least one cognitive function, the scanning of elements held in short term memory, is slowed in parkinsonism. This mnemonic slowing, like bradykinesia, is seen primarily in elderly parkinsonian patients. It is not readily explained as a motor phenomenon, as part of a generalized mnemonic or intellectual deficit, or as an artifact secondary to periodic extreme reaction times. The term bradyphrenia, used in early descriptions of parkinsonism, may be an apt descriptor of this deficit.

A frontal solution program is presented, based on the original work of Irons, published in 1970. The main drawback of the original frontal solution program that the complete front matrix has to reside in core has been overcome by ‘partitioning’ the front matrix. The programming strategy has been optimized to (a) minimize the number of I/O operations on the partitioned front‐matrix (b) optimize the speed of I/O transfer between high speed memory and slow peripheral (or secondary) storage media, and (c) make the program transportable and easily implementable on different types of computers, including mini‐ and micro‐computers.

The fastest parallel and pipeline computers presently being designed use interleaved memory systems with more than 16 individual memory units. A common difficulty in these machines is the alignment of data before it is arithmetically processed. Usually the arithmetic unit is used to preprocess the data. This may increase the computation time by a factor of two or more. This paper proposes a programmed memory preprocessing system which aligns the data before it is passed to the arithmetic processor.

A few classes of codes, suitable for error correction in high-speed memory systems, are presented. The codes have relatively simple parallel decoding nets. The codes may be used for the correction of both temporary and catastrophic errors.

The logical, or system, organization of a buffered data storage system designed expressly for non-stationary randomly arriving data is described. The system makes use of multiple levels of buffering. Simulation on a digital computer is used as a design technique. The system was evaluated for an input arrival distribution expected from Columbia University's Nevis Neutron Velocity Spectrometer. It was shown that the amount of high speed memory required can be reduced by factors of 100, or more, when compared with more conventional single level buffer storage systems.

A ferrite core memory system organization is discussed which offers a significant improvement in performance as well as a lower cost potential in larger memory sizes. Significant differences relative to other memory organizations are presented. The diode decoded drive system is discussed in some detail, presenting a frequency domain approach to memory system resonances. A particular system is described and the directions for future system development are presented.

Two groups of 8 Ss memorized three lists of consonental phonemes. The length of the memorized lists (M) was one, two, and four phonemes. Test words were presented, and reaction time (RT) for S to say whether or not the word started with a member of the memorized list was measured. RT increased with M. In one group, the phonemes comprising the memorized sets were dissimilar. RT increased linearly with M for that group. In the other group, the phonemes comprising the sets were similar. The function relating RT to M appeared to deviate from linearity. Even after extended practice, all the evidence was consistent with a somewhat modified serial model of memory retrieval.

This note describes a new technique—Radix Exchange—for sorting data internal to the high speed memory of an electronic binary digital computer. The technique is faster than Inserting by the ratio (log 2 n )/ n for sorting n = 2 c items with values distributed evenly in the range 0 to 2 c — 1. Its speed compares favorably with internal merging and it has the significant advantage of requiring essentially no working area in addition to that storage for the data being sorted and the instructions comprising the Radix Exchange routine itself. The nomenclature used is, in most cases, that of E. H. Friend [1].