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1. Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

4. CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

5. NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2

7. Design-technology co-optimization overview of CFET architecture

8. NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector

9. Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO2/HfO2 Gate Dielectrics

11. Low-Capacitance, High-Speed O-band GeSi Quantum-Confined Stark Effect Electro Absorption Modulator

15. Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices

16. Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

17. Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO2/HfO2 Gate Dielectrics

18. Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs

19. Process-induced charging damage in IGZO nTFTs

22. Towards nonvolatile magnetic crossbar arrays: A three-dimensional-integrated field-coupled domain wall gate with perpendicular anisotropy.

27. Impact of packaging stress on thinned 6T SRAM die.

36. Stacked-Nanowires and FinFET Transistors: Guidelines fo the 7nm Technology

37. Controlled domain wall pinning in nanowires with perpendicular magnetic anisotropy by localized fringing fields.

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