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In order to achieve reliability study in large and complex analog and mixed signal (AMS) circuits and systems, it is required to develop effective reliability-aware design methodologies and exploration tools. This paper discusses two aging mechanisms: hot carrier injection (HCI) and negative bias temperature instability (NBTI) and their effect on 65 nm CMOS integrated circuits and systems (ICs). We propose an aging-aware cross-layer approach to comprehensively evaluate aging induced performance degradation at the abstraction (system) level. This approach is composed by hierarchical aging analysis at transistor/circuit level, block failure analysis at abstraction level and system-level aging considerations, which can essentially highlight sensitive blocks for circuit designers. This approach is demonstrated with a continuous-time (CT) sigma–delta ( Σ Δ ) modulator. Analog loop filter and clock distributor are studied with failure boundary and transistor level aging simulation. The aging investigation approach reports system level aging-aware consideration of these building blocks. Results show that amplifiers in analog loop filter have enough margin to cope with aging induced degradations. However, aging risk exists in clock circuits, especially when implementing with high V t transistors. NBTI induced clock jitter from clock distributor can influence clocked block in CT Σ Δ modulator and degrade signal-to-noise ratio (SNR).

The design of a new digital radio receiver for radio astronomical observations in outer space is challenged with energy and bandwidth constraints. This paper proposes a new solution to reduce the number of samples acquired under the Shannon–Nyquist limit while retaining the relevant information of the signal. For this, it proposes to exploit the sparsity of the signal by using a compressive sampling process (also called Compressed Sensing (CS)) at the Analog-to-Digital Converter (ADC) to reduce the amount of data acquired and the energy consumption. As an example of an astrophysical signal, we have analyzed a real Jovian signal within a bandwidth of 40[Formula: see text]MHz. We have demonstrated that its best sparsity is in the frequency domain with a sparsity level of at least 10% and we have chosen, through a literature review, the Non-Uniform Sampler (NUS) as the receiver architecture. A method for evaluating the reconstruction of the Jovian signal is implemented to assess the impact of CS compression on the relevant information and to calibrate the detection threshold. Through extensive numerical simulations, and by using Orthogonal Matching Pursuit (OMP) as the reconstruction algorithm, we have shown that the Jovian signal could be sensed by taking only 20% of samples at random, while still recovering the relevant information.

This paper presents a 120 dB Stacked analog to digital (A/D) converter dedicated for radio astronomy. The design of the chain of cascaded amplifiers preceding the A/D converters was performed in a 1.2 V 65 nm CMOS process. Simulation results showed that the designed chain of three cascaded amplifiers has an overall gain of 90 dB (30 dB each) over 100 MHz of bandwidth. The paper proposes also a calibration technique that copes with the phase and gain mismatches between channels allowing thereby to reach the minimum required SNR of 30 dB over all the input range.

In order to reduce power consumption and limit the amount of data acquired and stored for astrophysical signals, an emerging sampling paradigm called compressed sensing (also known as compressive sensing, compressive sampling, CS) could potentially be an efficient solution. The design of radio receiver architecture based on CS requires knowledge of the sparsity domain of the signal and an appropriate measurement matrix. In this paper, we analyze an astrophysical signal (jovian signal with a bandwidth of 40 MHz) by extracting its relevant information via the Radon Transform. Then, we study its sparsity and we establish its sensing modality as well as the minimum number of measurements required. Experimental results demonstrate that our signal is sparse in the frequency domain with a compressibility level of at least 10%. Using the Non Uniform Sampler (NUS) as receiver architecture, we prove that by taking 1/3 of samples at random we can recover the relevant information.

Distorsion and attenuation occuring during track and hold transition are challenging for Track-and-hold amplifier (THA) with bandwidth larger than 10GHz. Moreover, single-ended to differential conversion is mainly required for radar applications. A single-ended/differential wideband THA circuit with a specific clock delay line buffer is proposed. The demonstrated technique is robust and results in a low distortion and low attenuation sampling operation for an input power of −5dBm over the entire bandwidth. The validity of the concept has been demonstrated by a circuit realized in 130nm SiGe BiCMOS. Furthermore, the proposed compensated balun allows to achieve a low phase difference (±4.5 o) and gain variation (0.25dB) in the [1–26]GHz frequency band. An effective bandwidth of 26GHz was measured with a Total-Harmonic-Distorsion (THD) of −51dB@10 GHz and −39dB@20 GHz at a sampling rate of 2.5 GS/s.

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.

In this paper we propose a digital blind calibration scheme for Time-Interleaved ADCs based on transfer function mismatch which corrects gain, time-skew and bandwidth mismatch errors. The estimation of mismatches uses an adaptive filtering structure with a lowpass filter combined to a fractional delay filter. The compensation is based on the development of a matrix approach to cancel the effect of mismatches. The algorithm was tested with a two-channel 14-bits ADCs board connected to a FPGA and the results show the effectiveness of the technique.

The estimation of mismatch-induced errors between the channels of a Time-Interleaved ADC is crucial for implementing an efficient calibration method. This step is often done with the assumption that all the noise sources have a white gaussian distribution. In this paper we analyze the statistical properties of noise components in wideband ADCs in terms of Probability Density Function (PDF) and Power Spectral Density (PSD) and discuss some conditions of whiteness.

International audience; The bootstrap technique is known to increase the linearity of Sample and Hold (S/H) circuit by reducing the input signal dependency of the transistor-switch resistance. But some nonlinearities remain due to parasitic capacitances, mobility degradation and back gate effect resulting in a second order harmonic spurious which can be reduced with a differential architecture. However mismatch between channels limits this technique. In this paper, we provide a general framework to analyze the residual nonlinearity in bootstrapped S/H. Statistical laws are also provided converting harmonic distortion specifications into matching requirements for differential sampling and therefore provide key rules for S/H designers.

International audience; A step-by-step simulation methodology for large-bandwidth Track-and-hold (T/H) microwave circuit is proposed. A T/H circuit is characterized accurately under the Cadence c environment. With the consideration of a specific windowing function, linearity simulation analysis could be done effectively. Moreover, the use of an input frequency generation function, in accordance with theoretical calculation, allows to treat the entire input bandwidth (BW). A simulated switched emitter follower (SEF) structure in a 0.13-µm SiGe BiCMOS technology with 24 GHz effective bandwidth and a 4 GS/s clock illustrates our methodology.

International audience; We introduce the design and simulation results of a stacked ADCs architecture that allows the implementation of a wideband and high dynamic range radio astronomy receivers. This work focus on the capabilities of this architecture to make a significant dynamic range enhancement compared to single-ADC based receivers. A detailed analytical analysis of the power consumption shows that this architecture stretches the bandwidth of the receiver up to 100 MHz while being very power efficient. Furthermore, its excellent time-frequency resolution makes this architecture very attractive for spatial exploration missions.

Noise-immunity of a logic gate or a circuit is now an important design criterion with dimension scaling to nanometers. Two noise-immune design structures based on Markov random field (MRF) have been proposed in [1], [2] and [3]. These design structures can achieve an excellent noise-immunity but with a large number of redundant transistors. In this paper, a general noise-immune design structure easy to implement has been proposed. It can achieve nearly the same noise-immunity as Master-and-Slave MRF (MAS MRF) [3] but with a significantly less area penalty. Basic logic gates are simulated and comparison of different circuits based on different design structures is presented. These simulations are based on the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [4] and ST 65nm CMOS models.

Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ageing effects and process variations. BSIM4 transistor physical parameters are investigated. The non-dominated sorting-based multi-objective evolutionary algorithms is used to find the worst-case aged circuit performances. This approach is studied with a two stage Miller-operational-amplifier (Op-Amp) with 65nm CMOS technology. Simulation results show that the Op-Amp is HCI non-sensitive but suffer from NBTI degradation. Compared to traditional Monte-Carlo method, simulation time is reduced to 40%, with a trade-off of only 0.05% to 1.7% accuracy loss.

International audience

International audience; A low power and low cost WLAN/WiMAX RF front- end requires more advanced CMOS technologies whose transistor parameters degradation is becoming worse. Few published works has presented the reliability results for RF circuits. In order to fill this gap, we develop a new synthesis methodology for reliable RF front-end design using the design example of a reliable BLIXER. The first steps of our synthesis methodology is a transistor ageing simulation. Then, we calculate an estimation of the circuit performance and ageing using the circuit design equations and the total derivatives. Thus, we can find the required bias and sizing improving the circuit reliability. The simulation results of the typical circuit are coherent with the WLAN/WiMAX RF front-end specifications. Despite the integrated process variability and mismatch, we observe that 96.4 % of the simulation runs have Gain >; 10.0 dB, and 92.1% of the simulation runs have NFmax

The design for reliability concept is already in use on digital circuits, but not systematically in use on AMS or RF circuits. A reliable circuit design demands knowledge of the physical degradation and models to analyze the reliability in earlier stages. Also, it needs to be simple enough to be used on the redesign. In this work, we propose and validate an AMS and RF circuit design for reliability method. In order to investigate our method, we have designed a 5–3 NOR interpolative Digital Controlled Oscillator (DCO) near 1 GHz applications. This design example has presented 1.4% decrease of oscillation frequency, 0.2% decrease of phase noise for a 1 MHz off-set, and 2.1% decrease of power consumption after 10 years of degradation. According with the trends presented in Table I, we estimate that the f osc ageing degradation was improved of 13 % by applying the design for reliability method.

In this paper we present a merged Digitally Controlled Oscillator DCO and Time To Digital Converter TDC architecture. The DCO is a nine-stage interpolative ring made by NOR cells. It is designed for TV applications and it is implemented in 65nm CMOS process. The oscillator has a large frequency range, from 50MHz to 500MHz, and a 28 × 39/Ltm2 core area. It consumes 1mA from 1.2V power supply, and it has −120dBc/Hz@5MHz phase noise for 420 MHz carrier frequency. The oscillator states are directly used to measure the delay between input and output clocks. The resulting TDC is compact, very economic in power consumption and it has a resolution that is equal to 1/18 of the oscillation period. The DCO and the TDC are used in an All Digital Phase Locked Loop ADPLL.

Radio frequency (RF) products are very demanding in terms of technology developments. Reliability will be one of the most important challenges for the semiconductor industry during the following years. This work presents a wideband low noise amplifier (WBLNA) designed in CMOS 65 nm, its model for reliability estimation, and simulated results of fresh and aged devices. The WBLNA failure, defined in this work as the amount of degradation to have 3 dB gain loss or 10% bandwidth reduction, has been found for HCI I D , SBD and EM degradations. The most important simulated reliability degradation results have been highlighted. Therefore, the design for reliability concept can be systematically applied in the RF front-end circuits, and it has helped with WBLNA reliability improvement.

Deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and an FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.

The layout synthesis of analog circuits remains today a complex task difficult to automate. Various strategies are used, from a completely full-custom design up to an automated synthesis taking into account analog constraints. One popular technique developed to help the analog layout synthesis is the use of procedural design of basic cells. These cells are afterwards assembled either manually or using other CAD tools. The device generators described in this paper are developed to enhance layout design productivity of analog cells. These generators are written in language Skill for the Opus-Cadence framework. They cover the most common devices: resistors, capacitors, inductors, various transistor shapes, differential pairs and current sources. The context and the objectives of this work, the development strategy and the main functionalities are presented. Finally, an example is given. These generators have been successfully used to design several circuits.

Abstract To evaluate the field of application of in situ combustion in consolidated reservoirs, a new experimental set-up has been designed for analyzing the specific features of in situ combustion in core materials. In order to perform experiments under realistic reservoir conditions, new technologies were applied on the building of this physical model and contributed largely to demonstrate the feasibility of the combustion process in core materials. In particular, different solutions were tested to prevent fluids from by-passing the porous medium during combustion tests. It was found that cores covered with thin multi-layer coatings were able to support large temperature gradients and high differential pressures between the inlet and the outlet of the core. A new special setting was designed to seal the pressurized annular space between the coated core and the external enclosure. The core is equipped with narrow heating collars and the set-up is combined with a transverse heat losses control system as well as with computerized data acquisition and processing of the experimental results. The tests were performed with sandstone cores having different permeabilities. The effects of pressure and airflow rates were studied with heavy-oil-saturated cores. Successful results obtained with a 850 mD permeability sandstone show that the fuel availability and the air requirement are affected very slightly by these parameters. Later combustion tests performed with initial gas and/or water saturations and cores having larger permeabilities show, under certain conditions, steadily moving, self-sustaining combustion processes. A discussion concerning the relative effects of porosity and packing properties (specific surface area sand grain distribution, cementation) on the fuel laydown is presented. These results will contribute largely to evaluating the process under actual field conditions. Introduction Several papers have been published, in the last 20 years on in situ combustion tube experiments to evaluate the field of application of this complex process. These lab works concern generally the study of in situ combustion in unconsolidated matrix. Recently, Sibbald et al. presented a paper(3) describing combustion experiments performed in a system using both unconsolidated and consolidated core materials. The aim of this paper is to describe the lab work done at the Institut Francais du petrole (I.F.P.) to study the specific features of in situ combustion in core materials under realistic conditions. For this purpose, new equipment was designed at I.F.P. for this research. New technologies were applied in the building of this physical model, which largely helped demonstrate the feasibility and the reproducibility of the combustion process in core materials. This paper describes the main features of the equipment and the results obtained by a significant number of air combustion tests with four different cores and one oil having a sufficiently high specific gravity (0.96). The effects of pressure, air flow rates, water and gas saturations are also shown. Equipment-Main Features Core Coverings To prevent fluids from by-passing the core during the experiments and to take into account the heat transfer problems generated by the exothermic reactions, several technological solutions were tested.

Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

An ideal radio communication receiver places the analog to digital conversion just after the antenna. It is an objective in a “software radio” perspective. The available silicon technologies do not provide the performance required by this application. We are able to evaluate the present limits and the gap between these limits and the ideal solution proposed. In this paper, we describe the present possibilities in terms of receiver architectures and we deduce theAdc specifications. Then we analyse differentAdc architectures adapted to this application. The choice is mainly between pipeline and sigma- deltaAdc. We compare them in terms of power consumption and we introduce a factor of merit. The future technologies will have an impact onAdc performance. Superconductor technology applied toAdc may be a solution and it is analysed at the end of this paper.

Analog to information converter (AIC) is an energy efficient acquisition system based on Compressed Sensing (CS). This paper presents a new design of an AIC architecture named CS based Non Uniform Sampler (CS-NUS) for acquiring astrophysical signals. The aim is to evaluate its potential power consumption gain against conventional Analog to Digital Converter (ADC). The basic idea behind the NUS is to get samples randomly so that the average sampling frequency is below the conventional Nyquist rate. To do so, we have designed a pseudorandom non uniform clock generator (PNCG) to control a 10bit successive Approximation Register ADC (SAR ADC) in a 65nm CMOS technology. By taking advantage of the CS theory, the designed AIC digitize only 18 % of samples at random while consuming 5 times less than a conventional Nyquist-rate ADC.