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In this paper, a method for the design of analog-to-digital converters is presented. This method computes the sizes of the different components (transistors, capacitors, etc.) in a predefined ADC topology so that the design specifications are met in the desired process technology. The method is based on formulating the ADC design constraints such as specifications on power, signal-to-noise ratio (SNR), area, and sampling frequency in special convex form in terms of the component sizes of the ADC and intermediate design variables. More specifically, the problem of sizing the components of the ADC are cast as a geometric program. Therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. Very efficient numerical algorithms are then used to solve the resulting geometric program and to compute the component sizes of an ADC that meets the desired specifications. The synthesis method is fast, and determines the globally optimal design; in particular, the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. This paper introduces the concept of hierarchical problem formulation within a geometric programming framework. This modular formulation allows a high reuse of the ADC posynomial model. (6 figures, 25 refs.), Availability: Pub. in Proceedings of the IEEE Int'l Conference on Computer Aided Design, 10 Nov 2002.

We present a scalable analytical model for on-chip transformers that is suitable for design optimization and circuit simulation. We also provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient (k). The model agrees very well with measurements for a variety of transformer configurations.