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This work introduces a material and method for high-volume, low-temperature, screen printing of self-biased magnetic films made from a composite of M-type strontium ferrite SrFe12O19 (SrM) particles and polydimethylsiloxane (PDMS). The magnetic particles are aligned under a dc magnetic field, while the PDMS is cured at 75 °C, making this fabrication process compatible with semiconductor and printed-circuit-board substrates. Aligned composites with estimated SrM particle volume percentages of 14 vol.%, 20 vol.%, and 27 vol.% are fabricated, as well as an unaligned 14 vol.% composite for comparison. X-ray diffraction (XRD) and scanning electron microscopy (SEM) are used to examine the structure and composition of the composites. Furthermore, vibrating sample magnetometer and ferromagnetic resonance (FMR) measurements are performed to determine their dc and ac magnetic properties. Results show that the aligned composites have magnetic textures between 1.47 and 1.95, crystalline anisotropies between 1860 and 1960 kA/m, FMR frequencies of 45.5–45.9 GHz, and FMR linewidths between 3400 and 3500 Oe, indicating the potential for these materials in self-biased, non-reciprocal device applications. The analysis identifies that increased particle loading and better particle alignment may further improve these films by decreasing the linewidth.

Heterogeneous integration of IC chiplets into systems on a chip (SoC) is further revolutionizing the semiconductor industry. This letter introduces a metal embedded chiplet assembly for microwave integrated circuit (MECAMIC) technology that uses high-scaled GaN HEMT chiplets. MECAMIC relies on the cointegration of transistor chiplets with passive interposers using an embedding backside metal process. We report the development of standardized 40-nm AlGaN/GaN HEMT chiplets to rapidly prototype GaN circuits up to $W$ -band by combining advances in $e$ -beam gate processes and massively parallel singulation techniques. GaN chiplets with $f_{\mathrm {T}} > 110$ GHz and $I_{\mathrm {max}} > 1.3$ A/mm were fabricated in yielded quantities exceeding 50000 per $4\prime\prime$ wafer. Simulation and experimental results of single-stage MECAMIC circuits with $4\,\,\mu \text{m}\,\,\times 37.5\,\,\mu \text{m}$ device chiplets demonstrated 6.8-dB gain at 77 GHz. The MECAMIC technology not only optimizes the GaN wafer utilization but also provides the ability to incorporate other technologies, offering unique design flexibility at millimeter wave.

This letter provides an overview of the metal-embedded chiplet assembly for microwave integrated circuits (MECAMICs) technology. MECAMIC is a 2.5-D wafer-level packaging approach that provides seamless heterogeneous integration capabilities of compound semiconductor transistors (e.g., GaN HEMTs) with passive components and interconnects using a backside metal embedding process. The chiplets are embedded in through-interposer cavities, and the backside metallization locks the chiplets into position while providing dc and RF ground for the high-frequency circuits. With this hybrid manufacturing approach, high-performance RF ICs can: 1) be designed using the best transistor technology for the function; 2) be fabricated in short cycle times through hybrid manufacturing; and 3) compete performancewise with monolithic circuits. We demonstrated an $X$ -band power amplifier circuit realized in MECAMIC with a saturated output power of 31 dB and a peak power added efficiency of 54%, which compared favorably to its monolithic GaN monolithic microwave integrated circuit (MMIC) counterpart. The MECAMIC process cycle time was $4.5\times $ faster than the monolithic process.

This paper presents the radio frequency (RF) benefits of a heterogeneous integration technique for multi-chip modules. Passive components, such as lumped metal–insulator–semiconductor (MIS) and ceramic capacitors, as well as coupler circuits implemented on alumina substrates, are integrated in a metal-embedded chip assembly (MECA) process together with GaN monolithic microwave-integrated circuits (MMICs) in a way that provides a common RF and thermal ground. Simulations show that photolithographically defined interconnects can outperform wire bonds from 10 to 100 GHz. The interconnect layer of the MECA process forms bridge transmission lines with lower loss and comparable dispersion to microstrip lines, and with 35% higher characteristic impedances, validated by measurements up to 25 GHz. Microstrip Lange and branch-line couplers are designed partially on alumina and completed with MECA interconnects during the integration process, resulting in good performance in agreement with simulations. Finally, measurements of a GaN power amplifier (PA) MMIC integrated into the MECA process show gain and power-added efficiency (PAE) improvements of up to 3 dB and 3.2 percentage points, respectively.

In this work, we report a K a band self-biased microwave circulator using a strontium hexaferrite (SrM) / polydimethylsiloxane (PDMS) nanocomposite fabricated with a low-temperature (70 °C), packaging-compatible, screen-printing process. The magnetic composite shows a ferromagnetic resonance frequency (FMR) of 44.3 GHz. A millimeter wave circulator completely embedded in a Rogers 5880 substrate with a thickness of 254 µm and a total area of 33 mm2 is designed, fabricated, and characterized. At an operational frequency of 37.2 GHz, the measured insertion loss (IL) and isolation (IS) of the circulator are 5.4 dB and 22.2 dB, respectively. The measurement results match with the simulation results from High Frequency Structure Simulator (HFSS) and compare favorably with those of other magnetic circulators from literature.

Monolithic integration of high-frequency magnetic components such as hexaferrite circulators at the wafer scale can lead to a significant improvement in radio frequency (RF) circuit performance and functionality. However, current methods to monolithically integrate hexaferrite films, such as liquid phase epitaxy, require high temperature (> 900 °C) annealing to create crystalline alignment, which is not compatible with integrated circuit process temperatures ( 50 μm). In this work, we report the synthesis of pure phase, faceted, and high crystallinity hexaferrite [SrFe12O19] nano-platelets using a direct hydrothermal approach, followed by self-assembly of binder free SrFe12O19 films with high film density and high magnetic isotropy. The nano-platelets exhibit high staturation magnetization (~ 60 emu/g) and coercivity (Hc) of 815 Oe. The magnetic films exhibit dense nano-particle concentration and a magnetic squareness (Mr/Ms) of 0.7. They can be patterned using a selective assembly process through a thick photoresist mask. Thicknesses of up to 70 μm have been deposited on 4-in.-diamater wafers.

This paper describes the additional design dimension of a new heterogeneous packaging process, referred to as Metal-Embedded Chip Assembly (MECA). The interconnect layers of the process can be used as an additional degree of freedom for design and manufacturing of passive circuits for integrated RF front-ends. Transmission lines designed with the interconnect layer, referred to as bridge lines, with up to 35% higher characteristic impedances than their microstrip counterpart, are validated by measurements up to 25 GHz. An X-band Lange coupler with 3.9 GHz bandwidth is designed using MECA interconnects, with accurate bridge placement. Broadband measurements from 0 to 25 GHz show good agreement with simulations.

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.

HRL Laboratories has been developing a new approach for high resolution radar imaging on stationary platforms. High angular resolution is achieved by operating at 235 GHz and using a scalable tile phased array architecture that has the potential to realize thousands of elements at an affordable cost. HRL utilizes aperture coding techniques to minimize the size and complexity of the RF electronics needed for beamforming, and wafer level fabrication and integration allow tiles containing 1024 elements to be manufactured with reasonable costs. This paper describes the results of an initial feasibility study for HRL’s Coded Aperture Subreflector Array (CASA) approach for a 1024 element micromachined antenna array with integrated single-bit phase shifters. Two candidate electronic device technologies were evaluated over the 170 - 260 GHz range, GaN HEMT transistors and GaAs Schottky diodes. Array structures utilizing silicon micromachining and die bonding were evaluated for etch and alignment accuracy. Finally, the overall array efficiency was estimated to be about 37% (not including spillover losses) using full wave array simulations and measured device performance, which is a reasonable value at 235 GHz. Based on the measured data we selected GaN HEMT devices operated passively with 0V drain bias due to their extremely low DC power dissipation.

We provide an overview of key challenges and technical breakthroughs that led to development of highly scaled GaN HEMT's having ft > 400 GHz and fmax > 550 GHz and the corresponding IC process. These highly scaled GaN devices have 5 times higher breakdown voltage than transistors with similar high frequency RF power gain in other semiconductor systems (Si, SiGe, InP, GaAs). We also report performance of the first generation of MMIC power amplifiers (PAs) that utilize these highly scaled devices. The power added efficiency (PAE) of 59% measured at a frequency of 32 GHz, bias of 3 V and output power of 24.3 dBm of the first generation Ka-band MMIC PAs that were built using these highly scaled GaN devices, represent a significant improvement in PAE over values reported for other semiconductor technologies at this frequency band as well as for Ka-band MMICs built in lower frequency GaN nodes. Presented data suggest that highly scaled GaN transistors are excellent candidates for MMIC PAs for next generation 28 GHz, 39 GHz, and higher frequency 5G mobile bands, because they would greatly extend battery lifetime in mobile handsets, due to their superior PAE compared to competing semiconductor technologies.

We report the first generation of GaN MMIC circuits that are based on the latest generation of (ft > 320 GHz and fmax > 580 GHz) [1] GaN Transistors. The reported broadband Ka-band (27 GHz - 40 GHz) GaN LNA MMIC's have Noise Figure (NF) as low as 1 dB measured at a frequency of 37 GHz, NF 24dB of gain across 28 GHz- 39.2 GHz frequency range, and a very broad range of usable DC bias conditions (Vd: 0.6V - 4V; Pdc: 5 mW- 310 mW). This is to the best of our knowledge the lowest NF reported for GaN LNA in this frequency band.

We present the fabrication and experimental characterization of wafer-level-packaged GaN power HEMTs incorporating embedded copper thermal heat spreader and microfabricated interconnects for GaN-based RF front-ends. The packaging fabrication technology mainly relies on silicon micromachining, metal electroplating, and thermocompression bonding. The presented packaging approach simultaneously addresses thermal management, electrical interconnects, performance, and has size and cost advantages over conventional assembly approaches. Silicon-packaged GaN-on-SiC power switches with slanted field plate technology demonstrated comparable DC IV characteristics with on-wafer measurements (threshold voltage = 0.3 V, static on-resistance = 2 Ω.mm measured at gate bias voltage of 1.5V, and drain and gate leakage current < 10−6 A/mm at gate bias voltage of −2 V). The performance results of Si-packaged GaN devices were consistent with on-wafer measurements, indicating compatibility of the packaging technology with GaN power HEMTs.

We report a new wafer-level, low-cost, scalable RF front-end packaging approach that enables heterogeneous integration of GaN integrated circuits (IC) with other ICs (Si, SiGe, InP, GaAs etc) and RF passives in a 3D package that includes RF/DC interconnects and thermal management. This is achieved by forming a composite substrate utilizing double-side polished alumina wafers with embedded electroformed heat spreaders and through substrate vias. We call this composite substrate Integrated Thermal Array Plate (ITAP). Compared to conventionally mounted GaN power amplifier (PA) using AuSn and silver epoxy the ITAP pckaged X-band PA demonstrated 1.42x and 2x improvement in output power respectively (36.4 dBm, with 57% associated power added efficiency). By using a junction temperature (T j ) evaluation circuit we demonstrated that the ITAP reduces the T j by 40° when the dissipated power is 2W/mm or increases the power handling by 1.45x when the T j is held at 150°C. Using the same approach we are also reporting wafer-level packaged GaN power switches as well as thermal cycling and thermal shock test data that show no performance degradation.